Abstract: One method includes: (a) forwarding an input challenge to a prover at a start time, the input challenge having a time-stamp; (b) receiving a proof of storage responsive to the input challenge from the prover; (c) generating a new input challenge based on the proof of storage and forwarding the new input challenge to the prover; (d) repeating steps (b) and (c) resulting in a final proof; (e) receiving a proof result based on the final proof, the proof result having a time-stamp; (f) determining that the time between the start time time-stamp and the proof result time-stamp is less than a specified period of time; and (g) determining a winning prover from a plurality of candidate provers where a probability of a candidate prover being a winning prover is proportional to the candidate prover's assigned storage which is indicated at least in part by the candidate miner's proof result.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for replication-related protocols for decentralized networks. One method includes: receiving, at a prover, a file to be stored; encoding the file to be stored using an encoding function to produce an encoded stored file wherein the time to encode using the encoding function takes at least a minimum encoding time; receiving a challenge at the prover; producing a proof at the prover in response to the challenge within a verify time period, wherein the proof is determined in part by decoding the encoded stored file and wherein the verify time period is less than the minimum encoding time; and taking an action (e.g., rewarding a storage miner/prover) in response to the proof.

Abstract: A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A reconfigurable asynchronous logic cell comprises a set of one-bit buffers for communication with at least one neighboring cell, each buffer capable of having several states and configured for receiving input state tokens from neighboring cells and for transferring output state tokens to neighboring cells, and a one-bit processor configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, wherein the logic operation and the functional configuration of the buffers are reconfigurably programmable. A reconfigurable logic circuit comprises a plurality of reconfigurable logic cells that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic cells.

Abstract: A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.

Abstract: A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A reconfigurable asynchronous logic cell comprises a set of one-bit buffers for communication with at least one neighboring cell, each buffer capable of having several states and configured for receiving input state tokens from neighboring cells and for transferring output state tokens to neighboring cells, and a one-bit processor configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, wherein the logic operation and the functional configuration of the buffers are reconfigurably programmable. A reconfigurable logic circuit comprises a plurality of reconfigurable logic cells that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic cells.

Abstract: A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.

Abstract: A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.

Abstract: A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of tokens. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. A reconfigurable asynchronous logic element comprises a set of edges for communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring tokens to at least one neighboring cell, circuitry configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, and circuitry.

Abstract: A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of tokens. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. A reconfigurable asynchronous logic element comprises a set of edges for communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring tokens to at least one neighboring cell, circuitry configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, and circuitry.

Abstract: A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.