Abstract: For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.

Abstract: A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.

Abstract: A mechanism and method for software hint initiated prefetch is provided. The prefetch may be directed to a prefetch of data for loading into a data cache, instructions for entry into an instruction cache or for either, in an embodiment having a combined cache. In response to a software instruction in an instruction stream, a plurality of prefetch specification data values are loaded into a register having a plurality of entries corresponding thereto. Prefetch specification data values include the address of the first cache line to be prefetched, and the stride, or the incremental offset, of the address of subsequent lines to be prefetched. Prefetch requests are generated by a prefetch control state machine using the prefetch specification data values stored in the register. Prefetch requests are issued to a hierarchy of cache memory devices. If a cache hit occurs having the specified cache coherency, the prefetch is vitiated.

Abstract: A method and system for branch dispatching of instructions in a data processor. A processor having one or more buffers for storing instructions and one or more execution units for executing instructions is utilized. Each unit has a corresponding queue which holds instructions pending execution. First, a threshold level (selected maximum number of instructions in the instruction queue) is set. The current utilization measure for one or more execution units in the data processing system is determined. The current utilization measure is compared to the predetermined threshold value; and a speculative branch instruction is dispatched to a selected execution unit when the current utilization measure is less than the predetermined threshold value.

Abstract: A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.

Abstract: An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions.

Abstract: One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.

Abstract: A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requestor must wait for the data bus to become available and a token passed to the requestor. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.

Abstract: A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requester must wait for the data bus to become available and a token passed to the requester. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.