Abstract: Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.

Abstract: A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.

Abstract: Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.

Abstract: A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.

Abstract: Disclosed is an inrush current control circuit for controlling current into a high-current circuit block. The inrush current control circuit comprises a number of distributed switches and a digital control circuit coupled to at least one of the distributed switches. The digital control circuit is configured to switch a first group of the distributed switches in response to an enable/disable signal. The digital control circuit is further configured to switch a second group of the distributed switches after a first programmable delay. According to one embodiment, a method comprises switching a first group of distributed switches by a digital control circuit of an inrush current control circuit in response to an enable/disable signal, and switching a second group of the distributed switches by the digital control circuit after a first programmable delay, thereby resulting in regulation of a flow of an inrush current.

Abstract: Disclosed is an inrush current control circuit for controlling current into a high-current circuit block. The inrush current control circuit comprises a number of distributed switches and a digital control circuit coupled to at least one of the distributed switches. The digital control circuit is configured to switch a first group of the distributed switches in response to an enable/disable signal. The digital control circuit is further configured to switch a second group of the distributed switches after a first programmable delay. According to one embodiment, a method comprises switching a first group of distributed switches by a digital control circuit of an inrush current control circuit in response to an enable/disable signal, and switching a second group of the distributed switches by the digital control circuit after a first programmable delay, thereby resulting in regulation of a flow of an inrush current.