Abstract: A computer system implements a memory unit, which includes first DRAM devices, second DRAM devices, a first memory controller, and a second memory controller. Each of the first DRAM devices have a first individual memory capacity and each of the second DRAM devices have a second individual memory capacity. The first memory controller is in signal communication with the first DRAM devices and the second memory controller is in signal communication with the second DRAM devices. Each of the first DRAM devices and the second DRAM devices are selectively operable as one of an active DRAM device to stare application data or a spare DRAM device reserved to receive the application data from the active DRAM devices to dynamically over-provision a total memory defined by a sum of the first and second individual memory capacities.

Abstract: A computer-implemented method and system for affinity based optimization of persistent memory volumes. Responsive to receiving a request for a parent virtual PMEM device, a total memory capacity is apportioned amongst virtual persistent memory (PMEM) resources and physical memory resources. In accordance with a target affinity characteristic, a set of virtual central processor unit (CPU) sockets are assigned. Each virtual CPU socket is configured based on at least one physical central processor unit (CPU) core in conjunction with a subset of the virtual PMEM and physical memory resources. Child virtual PMEM devices are created for respective ones of the virtual CPU sockets, each of the child virtual PMEM devices being dedicated to the parent virtual PMEM device.

Abstract: A computer-implemented method and system for affinity based optimization of persistent memory volumes. Responsive to receiving a request for a parent virtual PMEM device, a total memory capacity is apportioned amongst virtual persistent memory (PMEM) resources and physical memory resources. In accordance with a target affinity characteristic, a set of virtual central processor unit (CPU) sockets are assigned. Each virtual CPU socket is configured based on at least one physical central processor unit (CPU) core in conjunction with a subset of the virtual PMEM and physical memory resources. Child virtual PMEM devices are created for respective ones of the virtual CPU sockets, each of the child virtual PMEM devices being dedicated to the parent virtual PMEM device.