Abstract: The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.

Abstract: The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.

Abstract: A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.

Abstract: An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.

Abstract: A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.

Abstract: An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.