Abstract: The present invention is directed to a simulation testbench 10 which includes a circuit under test 14 and a plurality of test models 12 designated 1 through N. The test models 12 include at least one of a driver and a monitor. The drivers selectively apply stimuli to the circuit under test 14, and the monitors observe responses to the stimuli from the circuit under test 14. A single controller 16 is provided for the plurality of test models 12. The controller 16 has an instruction source 18 including a list of commands which control the plurality of test models 12. The commands are routed from the instruction source 18 over a model control bus 24 to the plurality of test models 12.

Abstract: A design-level description of a circuit is processed to incorporate testability functions in the form of scan chains. The design-level description may be a Register Transfer Level (RTL) description in accordance with the VHDL standard. The design-level description includes processes describing operations of the circuit. The processes are analyzed to identify data carriers in the design-level description which correspond to flip-flops or other specified elements in the circuit. The specified elements are organized into scan chains, which are then allocated to appropriate modules of the circuit. Scan ordering and scan insertion operations are performed separately on each of the modules. The scan ordering operation is based on functional relationships between the data carriers in the processes associated with the modules. The functional relationships can include both word-level and bit-level dependencies. The scan insertion operation involves inserting scan assignment statements into the processes.