Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A high speed pseudo-, 8-, 16-, or greater, ported cache memory, and associated effective address generation scheme. Based upon either two-port building blocks, or twice as many single-port building blocks, which are interleaved, the cache memory is arranged as a functional equivalent to a true 8-, 16-, or greater ported interleaved cache memory.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: Compile and/or run time instruction scheduling is used in a multiprocessing system to reorder memory access instructions such that a strongly consistent programming model is emulated in a fashion transparent to the programmer. The multiprocessing system detects potential shared memory conflicts, avoiding these conflicts by restarting operation of the affected processing unit at a predetermined previous state, previously archived in a rollback register set, and resuming instruction execution from that state.

Abstract: A memory architecture and method of partitioning a computer memory. The architecture includes a cache section, a setup table, and a compressed storage, all of which are partitioned from a computer memory. The cache section is used for storing uncompressed data and is a fast access memory for data which is frequently referenced. The compressed storage is used for storing compressed data. The setup table is used for specifying locations of compressed data stored within the compressed storage. A high speed uncompressed cache directory is coupled to the memory for determining if data is stored in the cache section or compressed storage and for locating data in the cache.

Abstract: A CPU of a computer system utilizing a VLIW architecture comprises an instruction register, an instruction sequencing unit, a bank of data registers, a set of arithmetic/logic units (ALUs), and instruction decode logic. The bit positions in the instruction register correspond to a set of parcels or fields, each parcel corresponding to a different respective one of the ALUs. The operation, if any, performed by each ALU during a machine cycle is specified by the parcel corresponding to the ALU. Each parcel of an instruction may contain such information as an operation code (op code), source and destination registers, special registers, immediate data, storage addresses, etc. In order to reduce the total number of bits required to store an instruction, at least some of the bit positions required to specify such information to the instruction decode logic are implied by the position of the parcel within the instruction word. Preferably, multiple-way conditional branches may be specified in each instruction word.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A high speed register file is provided for use with Very Long Word Instruction (VLIW) and N-way superscaler processors. The high speed register file includes a selected number of copies of a general purpose register (GPR) building block. The GPR building block includes at least two interleaved sub-banks of registers. Each of the sub-banks includes a number N of write ports and a number M of read ports. The sub-banks are interleaved by write ports and have non-interleaved read ports.