Patents by Inventor David Asher

David Asher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210374057
    Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Inventors: Craig BARNER, David ASHER, Richard KESSLER, Bradley DOBBIE, Daniel DEVER, Thomas F. HUMMEL, Isam AKKAWI
  • Patent number: 11188466
    Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 30, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
  • Publication number: 20210366572
    Abstract: Disclosed are thermodynamic and multiplication methods concerning CRISPR-Cas systems, and apparatus therefor.
    Type: Application
    Filed: February 23, 2021
    Publication date: November 25, 2021
    Applicants: The Broad Institute, Inc., Massachusetts Institute of Technology, President and Fellows of Harvard College
    Inventors: Feng Zhang, Yinqing Li, David Arthur Scott, Joshua Asher Weinstein, Patrick Hsu
  • Patent number: 11170630
    Abstract: Aspects provide methods to discretely and intelligently make a user aware of a service or product offered by a subscriber without distracting the user with a full advertisement. More specifically, aspects provide methods and systems for selectively outputting an audio chime in response to a trigger event, wherein the audio chime provides an indication of a service or product offered by the subscriber. In response to a user's acceptance of the audio chime, a second chime, further engaging the user, is output.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 9, 2021
    Assignee: BOSE CORPORATION
    Inventors: David Asher, Todd Reily
  • Patent number: 11119929
    Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
  • Publication number: 20210035434
    Abstract: Aspects provide methods to discretely and intelligently make a user aware of a service or product offered by a subscriber without distracting the user with a full advertisement. More specifically, aspects provide methods and systems for selectively outputting an audio chime in response to a trigger event, wherein the audio chime provides an indication of a service or product offered by the subscriber. In response to a user's acceptance of the audio chime, a second chime, further engaging the user, is output.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: BOSE CORPORATION
    Inventors: David ASHER, Todd REILY
  • Publication number: 20200250088
    Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: Craig Barner, David Asher, Richard Kessler, Brad Dobbie, Daniel Dever, Tom Hummel, Isam Akkawi
  • Publication number: 20200183844
    Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
    Type: Application
    Filed: February 11, 2020
    Publication date: June 11, 2020
    Inventors: Richard E. KESSLER, David ASHER, Shubhendu S. MUKHERJEE, Wilson P. SNYDER, II, David CARLSON, Jason ZEBCHUK, Isam AKKAWI
  • Publication number: 20200097292
    Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: David Albert Carlson, Shubhendu Sekhar MUKHERJEE, Michael BERTONE, David Asher, Daniel DEVER, Bradley D. DOBBIE, Tom HUMMEL
  • Patent number: 10599430
    Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 24, 2020
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10558573
    Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 11, 2020
    Assignee: Cavium, LLC
    Inventors: Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
  • Patent number: 10445096
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10331500
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 25, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10282299
    Abstract: Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory requests originating from processor cores, including: comparing at least a portion of an address included in a memory request with tags stored in a cache to determine whether the memory request results in a hit or a miss, and comparing an entity identifier included in the memory request with stored entity identifiers to determine a matched entry. The cache configuration information associated with the entity identifier in a matched entry is updated based at least in part on a hit or miss result. The associated cache configuration information includes cache usage information that tracks usage of the cache by an entity associated with the particular entity identifier, and partition descriptors that each define a different group of one or more of the regions.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: May 7, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, David Asher, Wilson P. Snyder, II
  • Patent number: 10248420
    Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 2, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180373635
    Abstract: Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory requests originating from processor cores, including: comparing at least a portion of an address included in a memory request with tags stored in a cache to determine whether the memory request results in a hit or a miss, and comparing an entity identifier included in the memory request with stored entity identifiers to determine a matched entry. The cache configuration information associated with the entity identifier in a matched entry is updated based at least in part on a hit or miss result. The associated cache configuration information includes cache usage information that tracks usage of the cache by an entity associated with the particular entity identifier, and partition descriptors that each define a different group of one or more of the regions.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: Shubhendu Sekhar Mukherjee, David Asher, Wilson P. Snyder, II
  • Publication number: 20180293114
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.
    Type: Application
    Filed: September 7, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293070
    Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293113
    Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293100
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler