Patents by Inventor David Asher Friedman

David Asher Friedman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media
    Patent number: 9524264
    Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: December 20, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Yossi Amon, David Asher Friedman, Ben Levin, Sharon Graif
  • GENERATING COMBINED BUS CLOCK SIGNALS USING ASYNCHRONOUS MASTER DEVICE REFERENCE CLOCKS IN SHARED BUS SYSTEMS, AND RELATED METHODS, DEVICES, AND COMPUTER-READABLE MEDIA
    Publication number: 20150378955
    Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.
    Type: Application
    Filed: June 26, 2014
    Publication date: December 31, 2015
    Inventors: Yossi Amon, David Asher Friedman, Ben Levin, Sharon Graif