Abstract: A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of local bitlines operatively connected to the plurality of memory cells, and a local group periphery including a local bitline multiplexer operatively connected with the pairs of local bitlines of the corresponding local memory group; and a pair of global read bitlines operatively connected to outputs of the plurality of local group peripheries, a global read bitline multiplexer operatively connected to outputs of the plurality of pairs of the global read bitlines from the local memory group ways, and a bitline operational block operatively connected an output of the global read bitline multiplexer.

Abstract: A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of local bitlines operatively connected to the plurality of memory cells, and a local group periphery including a local bitline multiplexer operatively connected with the pairs of local bitlines of the corresponding local memory group; and a pair of global read bitlines operatively connected to outputs of the plurality of local group peripheries, a global read bitline multiplexer operatively connected to outputs of the plurality of pairs of the global read bitlines from the local memory group ways, and a bitline operational block operatively connected an output of the global read bitline multiplexer.

Abstract: A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.

Abstract: A method for remotely controlling an operated unmanned object, comprises defining of a set of control movements of an operator; selecting of minimal necessary signals to reliably acquire the operator's control movements; defining of a mapping of the control movements to commands for the operated unmanned object; sensing of operator's body movements; and transmitting of the minimal necessary signals corresponding to the operator's movements to the operated unmanned object.

Abstract: A system for interacting with a remote object comprising a wearable jacket for a user, two actuators for supporting arms of the user, motors for causing movements to at least one of a torso and the arms of the user, and sensors for measuring at least one of a force applied to the user and a position of the user, and a controller and data transmission device for communicating with the remote object.

Abstract: A wearable system for epileptic seizure detection, comprising an eyeglasses frame, with a left arm and a right arm configured to rest over the ears of an intended person wearing the eyeglasses, a first pair of electrodes located in the left arm, and a second pair of electrodes located in the right arm, the first pair of electrodes and the second pair of electrodes arranged such to be in contact with the skull of the intended person wearing the eyeglasses, and an EEG signal acquiring system integral to the left and right arms, connected to measuring outputs of the respective first pair and second pair of electrodes.

Abstract: A system for interacting with a remote object comprising a wearable jacket for a user, two actuators for supporting arms of the user, motors for causing movements to at least one of a torso and the arms of the user, and sensors for measuring at least one of a force applied to the user and a position of the user, and a controller and data transmission device for communicating with the remote object.

Abstract: A system for measuring blood pressure of a user that comprises an ElectroCardioGram (ECG) circuit with at least two ECG electrodes configured to obtain an electrical activity of a heart of the user by measuring the electrical signals detected at the at least two ECG electrodes as an electrocardiogram waveform, and a pulse oximeter circuit configured to obtain a pulse waveform corresponding to a blood flow on user's vessels. The system further comprises a processor that is in electrical contact with the electrocardiogram circuit and the pulse oximeter circuit. The processor is configured to simultaneously analyze the electrocardiogram waveform and the pulse waveform. The processor is further configured to identify a “Zero Voltage Crossing” point on the electrocardiogram waveform and to determine time delays from this point to respective different determined points of the pulse waveform; and to use the time delays to compute the blood pressure values.

Abstract: A method and device for reducing the computational complexity of a processing algorithm, of a discrete signal, in particular of the spectral estimation and analysis of bio-signals, with minimum or no quality loss, which comprises steps of (a) choosing a domain, such that transforming the signal to the chosen domain results to an approximately sparse representation, wherein at least part of the output data vector has zero or low magnitude elements; (b) converting the original signal in the domain chosen in step (a) through a mathematical transform consisting of arithmetic operations resulting in a vector of output data; (c) reformulating the processing algorithm of the original signal in the original domain into a modified algorithm consisting of equivalent arithmetic operations in the domain chosen in step (a) to yield the expected result with the expected quality quantified in terms of a suitable application metric; (d) combining the mathematical transform of step (b) and the equivalent mathematical operatio

Abstract: A system for measuring blood pressure of a user that comprises an ElectroCardioGram (ECG) circuit with at least two ECG electrodes configured to obtain an electrical activity of a heart of the user by measuring the electrical signals detected at the at least two ECG electrodes as an electrocardiogram waveform, and a pulse oximeter circuit configured to obtain a pulse waveform corresponding to a blood flow on user's vessels. The system further comprises a processor that is in electrical contact with the electrocardiogram circuit and the pulse oximeter circuit. The processor is configured to simultaneously analyze the electrocardiogram waveform and the pulse waveform.

Abstract: A method for classification of ECG beats into normal and different categories of abnormal beats. The method comprises the following steps, performed on a computing platform: a. performing a training phase comprising taking as an input one or more ECG beats that are pre-classified into the different categories, with each ECG beat decomposed into multiple features and defining membership functions for each beat category for each feature; b.

Abstract: A method for classification of ECG beats into normal and different categories of abnormal beats. The method comprises the following steps, performed on a computing platform: a. performing a training phase comprising taking as an input one or more ECG beats that are pre-classified into the different categories, with each ECG beat decomposed into multiple features and defining membership functions for each beat category for each feature; b.

Abstract: A method and device for reducing the computational complexity of a processing algorithm, of a discrete signal, in particular of the spectral estimation and analysis of bio-signals, with minimum or no quality loss, which comprises steps of (a) choosing a domain, such that transforming the signal to the chosen domain results to an approximately sparse representation, wherein at least part of the output data vector has zero or low magnitude elements; (b) converting the original signal in the domain chosen in step (a) through a mathematical transform consisting of arithmetic operations resulting in a vector of output data; (c) reformulating the processing algorithm of the original signal in the original domain into a modified algorithm consisting of equivalent arithmetic operations in the domain chosen in step (a) to yield the expected result with the expected quality quantified in terms of a suitable application metric; (d) combining the mathematical transform of step (b) and the equivalent mathematical operatio

Abstract: A method of organizing on-chip data memory in an embedded system-on-chip platform whereon a deterministic application needs to meet a guaranteed constraint on its functional system behavior is disclosed. In one aspect, the method includes: a) dividing the deterministic application into blocks one of which corresponds to a part of a subtask of the application, the block receiving input data and/or generating output data and including internal intermediate data for transforming the input data into the output data, b) splitting the internal intermediate data into state and non-state data, and c) putting the non-state data and a part of the state data in a protected buffering module being part of the data memory and being provided with an error detection and correction module, so that they are available for mitigating the effect of faults on the functional system behavior on-line while meeting the at least one guaranteed constraint.

Abstract: Method for automatic online delineation of an electrocardiogram (ECG) bio signal, said method comprising the detection of said bio signal through several leads followed by the combination of those multiple acquisitions into a single root-mean-squared (RMS) curve, said RMS curve being then undergoing a real-time single-lead delineation based on a mathematical processing.

Abstract: A method of organizing on-chip data memory in an embedded system-on-chip platform whereon a deterministic application needs to meet a guaranteed constraint on its functional system behavior is disclosed. In one aspect, the method includes: a) dividing the deterministic application into blocks one of which corresponds to a part of a subtask of the application, the block receiving input data and/or generating output data and including internal intermediate data for transforming the input data into the output data, b) splitting the internal intermediate data into state and non-state data, and c) putting the non-state data and a part of the state data in a protected buffering module being part of the data memory and being provided with an error detection and correction module, so that they are available for mitigating the effect of faults on the functional system behavior on-line while meeting the at least one guaranteed constraint.

Abstract: A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.

Abstract: A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.