Patents by Inventor David Auchere
David Auchere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12170262Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: GrantFiled: December 15, 2022Date of Patent: December 17, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
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Patent number: 12051681Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.Type: GrantFiled: July 13, 2021Date of Patent: July 30, 2024Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ALPS) SASInventors: Deborah Cogoni, David Auchere, Laurent Schwartz, Claire Laporte
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Patent number: 11756874Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.Type: GrantFiled: September 15, 2022Date of Patent: September 12, 2023Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Claire Laporte, Deborah Cogoni, Laurent Schwartz
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Patent number: 11557566Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: GrantFiled: March 31, 2020Date of Patent: January 17, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
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Patent number: 11482487Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.Type: GrantFiled: October 6, 2020Date of Patent: October 25, 2022Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Claire Laporte, Deborah Cogoni, Laurent Schwartz
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Patent number: 10897822Abstract: A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.Type: GrantFiled: March 11, 2020Date of Patent: January 19, 2021Assignee: STMicroelectronics (Grenoble 2) SASInventors: Fabien Quercia, David Auchere, Norbert Chevrier, Fabien Corsat
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Patent number: 10879583Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.Type: GrantFiled: December 10, 2019Date of Patent: December 29, 2020Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
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Patent number: 10811349Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.Type: GrantFiled: August 23, 2018Date of Patent: October 20, 2020Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Laurent Schwarz, Deborah Cogoni, Eric Saugier
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Publication number: 20200196433Abstract: A method includes attaching a discrete component on a circuit board with a first glue, attaching an integrated circuit to the circuit board using a third glue, and attaching a cap to the circuit board using a second glue. The first glue has a composition such that it does not interact electrically with the second glue and does not interact electrically with the third glue.Type: ApplicationFiled: November 21, 2019Publication date: June 18, 2020Inventors: David Auchere, Norbert Chevrier, Fabien Quercia, Asma Hajji
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Patent number: 10643970Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: GrantFiled: January 16, 2019Date of Patent: May 5, 2020Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
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Patent number: 10522899Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.Type: GrantFiled: June 25, 2018Date of Patent: December 31, 2019Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
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Patent number: 10257943Abstract: An electronic device includes a substrate having an external surface, and an integrated circuit over the external surface of the substrate. The substrate is provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links include an impedance-compensating inductor on an external surface of the substrate.Type: GrantFiled: March 20, 2018Date of Patent: April 9, 2019Assignee: STMICROELECTRONICS (GRENOVLE 2) SASInventors: David Auchere, Laurent Marechal
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Patent number: 10224306Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: GrantFiled: May 23, 2017Date of Patent: March 5, 2019Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
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Patent number: 10116037Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An en encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.Type: GrantFiled: August 4, 2017Date of Patent: October 30, 2018Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
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Publication number: 20180309187Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
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Patent number: 10103079Abstract: An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to the mounting face and is electrically connected to the electrical connection network. A primary encapsulation block embeds the integrated circuit chip and extends above and around the integrated circuit chip on the mounting face of the supporting substrate. An opening is provided in the primary encapsulation block to at least partially uncover an electrical contact. An additional wire made from an electrically conductive material has an end that is electrically connected to the electrical contact. An additional encapsulation block above the primary encapsulation block embeds the additional wire.Type: GrantFiled: July 25, 2017Date of Patent: October 16, 2018Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: Yvon Imbs, Laurent Schwarz, David Auchere, Laurent Marechal
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Patent number: 10062961Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.Type: GrantFiled: August 2, 2017Date of Patent: August 28, 2018Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Laurent Marechal, Laurent Schwarz, Yvon Imbs
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Publication number: 20180213654Abstract: An electronic device includes a substrate having an external surface, and an integrated circuit over the external surface of the substrate. The substrate is provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links include an impedance-compensating inductor on an external surface of the substrate.Type: ApplicationFiled: March 20, 2018Publication date: July 26, 2018Inventors: David Auchere, Laurent Marechal
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Publication number: 20180122770Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: ApplicationFiled: May 23, 2017Publication date: May 3, 2018Applicant: STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
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Patent number: 9949381Abstract: An electronic device includes a substrate having an external surface, and an integrated circuit over the external surface of the substrate. The substrate is provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links include an impedance-compensating inductor on an external surface of the substrate.Type: GrantFiled: July 14, 2014Date of Patent: April 17, 2018Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: David Auchere, Laurent Marechal