Abstract: Embodiments of the present disclosure relate to RF filter systems and methods. In some embodiments, an RF filter system includes a tuning signal injection circuitry, a tuning signal cancellation circuitry, and two FSLs. The RF filter system may receive one or more first RF signals that may include one or more signals of interest (SOIs) and one or more interfering signals. The RF filter system may receive one or more second RF signals that may include one or more tuning signals. The RF filter system may output one or more RF signals containing the one or more SOIs and attenuated versions of the interfering signals, without including the one or more tuning signals.

Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: A semiconductor die is aligned to a test probe by placing the semiconductor die onto a flat upper surface of a test stage with solder balls of the die facing upward, fluidizing motion of the die with reference to the test stage by pulsing gas between the die and the upper surface of the test stage, and coarse aligning the die with reference to the test stage by moving the die until adjacent edges of the die contact corner guides that are disposed on the test stage. Further, the method includes raising the test stage toward the test probe until an alignment feature of the test probe engages a first solder ball of the die, and fine aligning the die with reference to the test probe by continuing to raise the test stage until a second solder ball of the die fits into a test cup of the test probe.

Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: A semiconductor die is aligned to a test probe by placing the semiconductor die onto a flat upper surface of a test stage with solder balls of the die facing upward, fluidizing motion of the die with reference to the test stage by pulsing gas between the die and the upper surface of the test stage, and coarse aligning the die with reference to the test stage by moving the die until adjacent edges of the die contact corner guides that are disposed on the test stage.

Abstract: A method comprises circulating a heat transferring fluid in a substantially closed system including an interstice between a wafer and a chuck at a first pressure. The method further comprises pumping the fluid out of the interstice and increasing the pressure of the fluid to a second pressure. The method further comprises reducing the pressure of the fluid to the first pressure and returning the fluid to the interstice. In the system of the present invention, the fluid in the interstice transfers heat from the wafer to the chuck, or vice versa, by conduction. The presence of a conducting fluid in the interstice thereby decreases the resistivity of the interface, and enables more efficient heat transfer from the wafer to the chuck.

Abstract: A thermally conductive protective film or layer is applied to the backside surface of a semiconductor wafer prior to a subsequent dicing operation performed on the wafer to singulate the wafer into diced semiconductor chips, during which the thin thermally conductive film minimizes and prevents chipping and cracking damage to the wafer and diced chips.

Abstract: A method and apparatus for testing, the apparatus including: a probe array mounted on an inner portion of a gimbaled bearing, the inner portion of the gimbaled bearing having a spherical surface defined by a surface of a first sphere between two parallel small circles of the first sphere, a radius of the first sphere centered on a point on a top surface of the probe array; and an outer portion of the gimbaled bearing, the outer portion of the gimbaled bearing having a spherical surface defined by the surface of a second sphere between two parallel small circles of the second sphere, a radius of the second sphere centered on the point on the top surface of the probe array.