Patents by Inventor David B. Aldrich

David B. Aldrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7109838
    Abstract: An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth D. Brennan, Douglas A. Prinslow, David B. Aldrich
  • Patent number: 7001848
    Abstract: Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor and a second conductor for an electrical device formed in a semiconductor substrate, the method comprising the steps of: forming a dielectric layer (layer 226 of FIG. 2a) on the first conductor (conductor 222 of FIG. 2a), the dielectric layer having at least one opening which exposes the first conductor; forming a layer of an oxygen-sensitive material (layer 234 of FIG.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: February 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, David B. Aldrich, Stephen W. Russell
  • Patent number: 6958294
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: October 25, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Patent number: 6727185
    Abstract: A cleanup process that uses a dilute fluorine in oxygen chemistry in a downstream plasma tool to remove organic and inorganic polymeric residues (116).
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Antonio L. P. Rotondaro, David B. Aldrich, Eric C. Williams
  • Publication number: 20030207563
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Application
    Filed: June 9, 2003
    Publication date: November 6, 2003
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Publication number: 20030203642
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Application
    Filed: June 9, 2003
    Publication date: October 30, 2003
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Patent number: 6600208
    Abstract: A versatile system for reducing electromagnetic interference resulting from an inductor (300) formed within an integrated circuit is disclosed, including an inductor layer (310) having conductive elements (326) about its perimeter, first (306) and second (308) isolation layers disposed upon on opposite sides of the inductor layer and having conductive elements (326) about their perimeters, and first (302) and second (304) shield layers surrounding the first and second isolation layers, respectively, and coupled together by the conductive elements (326) of the isolation and inductor layers.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: July 29, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth D. Brennan, Douglas A. Prinslow, David B. Aldrich
  • Patent number: 6599829
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: July 29, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Publication number: 20020127840
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Application
    Filed: February 25, 2002
    Publication date: September 12, 2002
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Publication number: 20020096736
    Abstract: A versatile system for reducing electromagnetic interference resulting from an inductor (300) formed within an integrated circuit is disclosed, including an inductor layer (310) having conductive elements (326) about its perimeter, first (306) and second (308) isolation layers disposed upon on opposite sides of the inductor layer and having conductive elements (326) about their perimeters, and first (302) and second (304) shield layers surrounding the first and second isolation layers, respectively, and coupled together by the conductive elements (326) of the isolation and inductor layers.
    Type: Application
    Filed: September 10, 2001
    Publication date: July 25, 2002
    Inventors: Kenneth D. Brennan, Douglas A. Prinslow, David B. Aldrich
  • Publication number: 20020058355
    Abstract: An inductor integrated in a semiconductor device is disclosed, comprising a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.
    Type: Application
    Filed: September 10, 2001
    Publication date: May 16, 2002
    Inventors: Kenneth D. Brennan, Douglas A. Prinslow, David B. Aldrich
  • Patent number: 6246120
    Abstract: A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably. TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: June 12, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth D. Brennan, David B. Aldrich, Eden M. Zielinski, Peter S. McAnally
  • Patent number: 6074943
    Abstract: A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: June 13, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth D. Brennan, David B. Aldrich, Eden M. Zielinski, Peter S. McAnally