Abstract: Generating test input includes initializing a current pseudo-random value at a test input generator coupled to a circuit component. Write data is received from the circuit component. The following are repeated to generate next pseudo-random values as test input. The current pseudo-random value and the write data are retrieved. A next pseudo-random value is generated from the current pseudo-random value and the write data according to a generation function. The next pseudo-random value is transferred to the circuit component as the test input.

Abstract: One apparatus embodiment includes a patterned electrically conductive layer, a power source, and an actuator. The power source provides an electrical signal to the electrically conductive layer. The monitoring unit monitors the electrical signal and initiates an action based upon a change in the electrical signal.

Abstract: Circuit for performing arithmetic operations in a 32-bit architecture. The circuit includes a five stage shift and rotate circuit coupled between first and second 32-bit busses in the following sequence: an 8-bit shift and rotate circuit, a 16-bit shift and rotate circuit, a 1-bit shift and rotate circuit, a 2-bit shift and rotate circuit and a 4-bit shift and rotate circuit. For double word sized (32-bit) operands, the variously sized shift and rotate circuits may be selectively enabled to perform between 1-bit and 31-bit shift/rotate/pass operations. For byte sized operands, the 8-bit and 16-bit shift and rotate circuits are used to pre-process the operands while the 1-bit, 2-bit and 4-bit shift and rotate circuits are selectively enabled to perform the full range, i.e., 1-bit to 7-bit, of possible shift/rotate operations.