Abstract: A method and apparatus for providing data communication between stations on a network which optimizes the amount of resources required for a network switch. A first data frame is encoded with a source station identifier for the first station and a source switch identifier for the first switch. The first data frame is sent from the first switch to the second switch. A station list in the second switch is updated to indicate that the first station is associated with the first switch. Subsequent data frames having the same destination as the first switch are sent directly to the second switch. Any switch on the network need only identify the local ports attached to the switch, plus the number of switches on the network. The task of identifying all of the ports on the network is distributed across all switches on the network.

Abstract: A method and apparatus for providing data communication between stations on a network which optimizes the amount of resources required for a network switch. A first data frame is encoded with a source station identifier for the first station and a source switch identifier for the first switch. The first data frame is sent from the first switch to the second switch. A station list in the second switch is updated to indicate that the first station is associated with the first switch. Subsequent data frames having the same destination as the first switch are sent directly to the second switch. Any switch on the network need only identify the local ports attached to the switch, plus the number of switches on the network. The task of identifying all of the ports on the network is distributed across all switches on the network.

Abstract: A method and apparatus for providing data communication between a source station having multiple connections to a first switch and a destination station having multiple connections to a second switch. A trunk identifier to each port on the first switch and each port on the second switch. A data frame is encoded with the trunk identifier for an ingress port on the first switch. The data frame is sent to the second switch from the first switch. A list of egress ports for the destination station is obtained from a station list contained in the second switch. An egress port is selected from the list of egress ports based upon the source address, destination address and trunk identifier. The data frame is sent to the destination station through the selected egress port.

Abstract: A method and apparatus for providing data communication between stations on a network which optimizes the amount of resources required for a network switch. A first data frame is encoded with a source station identifier for the first station and a source switch identifier for the first switch. The first data frame is sent from the first switch to the second switch. A station list in the second switch is updated to indicate that the first station is associated with the first switch. Subsequent data frames having the same destination as the first switch are sent directly to the second switch. Any switch on the network need only identify the local ports attached to the switch, plus the number of switches on the network. The task of identifying all of the ports on the network is distributed across all switches on the network.

Abstract: A method and an apparatus providing data communications among network devices using tagged and untagged frame formats. In one embodiment, a virtual local area network (VLAN) is implemented using frames that may be transferred among network devices in both tagged and untagged formats. In one embodiment, the frames are transferred among network switches in an untagged format, independent of whether the source devices sent the frames in a tagged or untagged format. In addition, destination devices may receive frames in either a tagged or an untagged format, independent of whether the source devices originally send the frames a tagged or untagged format. Cyclic redundancy check (CRC) code information contained in the frames as originally sent is left unchanged when transferred among the switches of the VLAN, even though the frames may have been modified prior to transfer among switches.

Abstract: A method and an apparatus for adjusting an interpacket gap. In one embodiment, a plurality of network devices are tightly coupled together in series. Data is transmitted and received by the network devices in packets with interpacket gaps interposed between each packet. Buffers are included in each network device to serve as elasticity buffers for the data being transmitted between the network devices. The first upstream network device transmits interpacket gaps having an increased size. Downstream network devices may shrink increased size interpacket gaps to reduced size interpacket gaps if the internal buffers are filled to or above a high water mark. However, downstream network devices are not allowed to shrink the size of reduced size interpacket gaps that are received, even if their internal buffers are filled to or above the high water mark.

Abstract: An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.

Abstract: An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache.

Abstract: In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction.

Abstract: A method for simplifying Boolean AND-OR logic in a circuit synthesis system. Rules are associated with model instances representing circuit components and contained in a data base. During testing of an antecedent portion of a rule, a benefit value representing a decrease in pins or an improvement in timing is calculated and compared to the value of a "benefit variable", which represents a minimum acceptable benefit that must be gained from application of a rule. If a sufficient benefit will result from application of the rule, the rule is applied. Some rules simplify the circuit and then recursively call themselves. Some rules indicate other model instances in the data base, search the set of rules for rules applicable to that model instance, and apply the rule discovered during the search.

Abstract: An instruction decoder for a pipelined data processing unit simultaneously decodes two source specifiers and one destination specifier. All three of the specifiers can be register specifiers in which the specified operand is the content of a specified register. Any one of the specifiers can be a complex specifier designating an index register, a base register, and a displacement. Any one of the source specifiers can specify short literal data. Data for locating the two source operands and the destination operand are transmitted over parallel buses to an execution unit, so that most instructions are executed at a rate of one instruction per clock cycle. The complex specifier can have a variable length determined by its data type as well as its addressing mode. In particular, the complex specifier may specify a long length of extended immediate data that is received through the instruction buffer over a number of clock cycles.

Abstract: An instruction decoder generates implied specifiers for certain predefined instructions, and an operand processing unit preprocess most of the implied specifiers in the same fashion as express operand specifiers. For instructions having an implied autoincrement or autodecrement of the stack pointer, an implied read or write access type is assigned to the instruction and the decode logic is configured accordingly. When an opcode is decoded and is found to have an implied write specifier, a destination operand is created for autodecrementing the stack pointer. If an opcode is decoded and found to have an implied read specifier, a source operand is created for autoincrementing the stack pointer. A register or short literal specifier can be decoded simultaneously with the generation of the implied operand. Therefore some common instructions such as "PUSH Rx" can be decoded in a single cycle.

Abstract: A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing.

Abstract: A branch prediction is made by searching a cache memory for branch history information associated with a branch instruction. If associated information is not found in the cache, then the branch is predicted based on a predetermined branch bias for the branch instruction's opcode; otherwise, the branch is predicted based upon the associated information from the cache. The associated information in the cache preferably includes a length, displacement, and target address in addition to a prediction bit. If the cache includes associated information predicting that the branch will be taken, the target address from cache is used so long as the associated length and displacement match and the length and displacement for the branch instruction; otherwise, the target address must be computed.

Abstract: An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source operand, executes it and delivers the resultant data to memory. A "write queue" receives the write addresses of the destination operands from the operand processing unit, stores the write addresses, and delivers the stored preselected addresses to memory in response to receiving the resultant data corresponding to the preselected address. The addresses of the source operand is compared to the write addresses stored in the write queue, and the operand processing unit is stalled whenever at least one of the write addresses in the write queue is equivalent to the read address. Therefore, fetching of the operand is delayed until the corresponding resultant data has been delivered by the execution unit.

Abstract: An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes.

Abstract: To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit.