Patents by Inventor David B. Kramer
David B. Kramer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10241683Abstract: A data processing system includes a backup nonvolatile memory (NVM), a random access memory (RAM), and a controller. The RAM includes a plurality of partitions, each partition having a different corresponding backup frequency. The controller is configured to back up the contents of each partition of the RAM to the backup NVM in accordance with the corresponding backup frequency.Type: GrantFiled: October 26, 2015Date of Patent: March 26, 2019Assignee: NXP USA, Inc.Inventors: Frank Kelly Baker, Jr., David B. Kramer, Anirban Roy
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Patent number: 9733981Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.Type: GrantFiled: June 10, 2014Date of Patent: August 15, 2017Assignee: NXP USA, Inc.Inventors: Tommi M. Jokinen, Michael Kardonik, David B. Kramer, Peter W. Newton, John F. Pillar, Kun Xu
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Publication number: 20170115879Abstract: A data processing system includes a backup nonvolatile memory (NVM), a random access memory (RAM), and a controller. The RAM includes a plurality of partitions, each partition having a different corresponding backup frequency. The controller is configured to back up the contents of each partition of the RAM to the backup NVM in accordance with the corresponding backup frequency.Type: ApplicationFiled: October 26, 2015Publication date: April 27, 2017Inventors: FRANK KELLY BAKER, JR., DAVID B. KRAMER, ANIRBAN ROY
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Patent number: 9501442Abstract: In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.Type: GrantFiled: April 30, 2014Date of Patent: November 22, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: David B. Kramer, Thang Q. Nguyen
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Patent number: 9442870Abstract: A method and circuit for a data processing system (20) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (27-29) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.Type: GrantFiled: August 9, 2012Date of Patent: September 13, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
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Patent number: 9436626Abstract: A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.Type: GrantFiled: August 9, 2012Date of Patent: September 6, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
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Patent number: 9330054Abstract: A processor of a plurality of processors includes a processor core and a message manager. The message manager is in communication with the processor core. The message manager to receive a message from a second processor of the plurality of processors, to identify a classification rule for the message based on bits in a header of the message, and to create a queue identifier for the message using bits of a payload of the message, wherein the queue identifier is associated with a queue of the processor core.Type: GrantFiled: October 31, 2012Date of Patent: May 3, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Tommi N. Jokinen, David B. Kramer, Kun Xu
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Patent number: 9229884Abstract: A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., 14, 61) by executing a control instruction (47, 48) to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned device (14, 61) can determine if the access command can be performed based on local access control information.Type: GrantFiled: April 30, 2012Date of Patent: January 5, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
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Publication number: 20150355938Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.Type: ApplicationFiled: June 10, 2014Publication date: December 10, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Tommi M. Jokinen, Michael Kardonik, David B. Kramer, Peter W. Newton, John F. Pillar, Kun Xu
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Patent number: 9207979Abstract: A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.Type: GrantFiled: May 28, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: James C. Holt, Joseph P. Gergen, David B. Kramer, William C. Moyer
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Publication number: 20150347185Abstract: A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James C. Holt, Joseph P. Gergen, David B. Kramer, William C. Moyer
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Patent number: 9195621Abstract: A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.Type: GrantFiled: March 15, 2013Date of Patent: November 24, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Kun Xu, Tommi M. Jokinen, David B. Kramer
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Publication number: 20150317266Abstract: In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Inventors: DAVID B. KRAMER, Thang Q. Nguyen
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Patent number: 9152587Abstract: A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.Type: GrantFiled: May 31, 2012Date of Patent: October 6, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
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Patent number: 9128925Abstract: A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.Type: GrantFiled: April 24, 2012Date of Patent: September 8, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Tommi M. Jokinen, David B. Kramer, Kun Xu
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Patent number: 9054998Abstract: A source processor can divide each packet of a data stream into multiple segments prior to communication of the packet, allowing a packet to be transmitted in smaller chunks. The source processor can process the segments for two or more packets for a given data stream concurrently, and provide appropriate context information in each segments header to facilitate in order transmission and reception of the packets represented by the individual segments. Similarly, a destination processor can receive the packet segments packets for an ordered data stream from a source processor, and can assign different contexts, based upon the context information in each segments header. When a last segment is received for a particular packet, the context for the particular packet is closed, and a descriptor for the packet is sent to a queue. The order in which the last segments of the packets are transmitted maintains order amongst the packets.Type: GrantFiled: February 6, 2013Date of Patent: June 9, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Tommi M. Jokinen, David B. Kramer, Kun Xu
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Patent number: 8959278Abstract: A method of multicast data transfer including accessing a source address to a source location of mapped memory which stores source data, accessing multiple destination addresses to corresponding destination locations of the mapped memory, and for each of at least one section of the source data, reading the section using the source address, storing the section into a local memory of a data transfer device, and writing the section from the local memory to each destination location in the mapped memory using the destination addresses. Separate source and destination attributes may be provided, so that the source and each destination may have different attributes for reading and storing data. The source and each destination may have any number of data buffers accessible by corresponding links provided in data structures supporting the data transfer. The source data may be divided into sections and handled section by section.Type: GrantFiled: May 12, 2011Date of Patent: February 17, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Kun Xu, Tommi M. Jokinen, David B. Kramer
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Patent number: 8924784Abstract: An integrated circuit device includes a processor core, and a controller. The processor core issues a command intended for a first thread of a plurality of threads. The controller initiates de-allocates hardware resources of the controller that are allocated to the first thread during a thread reset process for the first thread, returns a specified value to the processor core in response to the first command intended for the first thread during the thread reset process, drops responses intended for the first thread from other devices during the thread reset process, completes the thread reset process in response to a determination that all expected responses intended for the first thread have been either received or dropped, and continues to issue requests to other devices in response to commands from other threads of the plurality of threads and processing corresponding responses during the thread reset process.Type: GrantFiled: April 12, 2012Date of Patent: December 30, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Kun Xu, David B. Kramer, Marie J. Sullivan
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Patent number: 8914550Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.Type: GrantFiled: March 15, 2013Date of Patent: December 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Tommi M. Jokinen, David B. Kramer, Kum Xu
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Publication number: 20140281043Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Tommi M. Jokinen, David B. Kramer, Kun Xu