Abstract: A video generation logic for a display controller includes a precoded PROM which combines visual attributes associated with the characters of information to be displayed on the display screen to produce multiple video control signals for modifying the dot pattern generation signal which is generated in response to character information stored in a refresh memory of the display controller. Visual attribute signals are used as an address to a video attribute generation PROM to retrieve a precoded data word associated with a particular combination of video attributes and the information contained in the retrieved data word is used to provide video control signals. Some of the video control signals are combined with the dot pattern generation signal to provide a video signal which is transmitted to the display monitor which displays the character information.

Abstract: A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.

Abstract: A refresh memory address generation apparatus for a video display controller is disclosed wherein rows of character information stored in a display refresh memory may be relocated without requiring the reconstruction of the display information as stored in the display refresh memory. A roll register and PROMs precoded to perform modular addition and multiplication are used to generate an address used to access the display controller refresh memory such that all but one stationary row of information on the display screen may be scrolled (rolled) up. The scrolling of the information on the display screen is accomplished without requiring movement of the display information in the refresh memory, and the only rewrite of information in the refresh memory is done to blank the one row of information which is vacated.

Abstract: A strobe generator in a data entry input device is responsive to an input strobe signal from a keyboard system to generate a strobe signal which is not affected by electrical noise produced by electrostatically or electromagnetically induced signals in the signal lines running between the keyboard system and the data entry device input logic. An accurate output strobe signal is generated by utilizing a retriggerable logic circuit to filter out noise signals of a duration shorter than a predetermined period. The predetermined period is chosen to be less than the minimum duration of a valid input strobe signal and greater than the duration of active noise signals. The strobe generator retains the output strobe signal in the active state by use of a flip-flop until the strobe generator receives a reset signal acknowledging that the output strobe signal has been sampled by the data entry device input logic.

Abstract: A data processing system remote monitor interface includes a first device which transmits different types of time-related information signals along multiple parallel channels to a second device for reception and combination into a different number of information signal outputs. The different types of digital information signals are synchronized by the first device prior to transmission to the second device. Components in the first device, the multiple parallel channels, and the second device are selected to maintain signal synchronization by minimizing signal skew thereby eliminating the necessity for signal resynchronization in the second device. The second device includes a receiver section which has a plurality of receivers. Each receiver operates to receive only one digital information signal and to pass the received signal onto its output.

Abstract: Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in either a frequency modulation (FM) mode or a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. Apparatus converts the time between successive digital signals into PROM addresses. The PROM address locations store coded signals identifying the data as binary ONE or binary ZERO signals.

Abstract: Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. A counter in the adapter starts to count when the adapter receives a digital signal. The count is transferred to a register and the counter presets when the adapter receives the next digital signal. The count is indicative of the time between the successive digital signals and should be representative of multiples of an integer. The count signals stored in the register address a read only memory whose output signals preset the counter to a value to compensate for the difference between the expected time and the actual time between the successive digital signals thereby reducing the read error rate.

Abstract: A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus.

Abstract: A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.

Abstract: A processing unit includes emulation apparatus which operates to execute instructions of a target system, one of a plurality of ways depending upon the options and features of the target system being emulated. The options, features and characteristics of the target system for which the program was originated is defined by the different bits of an option mask word stored within the emulation apparatus. Initially, upon switching to an emulation mode of operation, the emulation apparatus under microprogram control is operative to store signal representations of the option mask word in one of its storage registers. The signals from the stored option mask word are applied to different portions of the emulation apparatus for conditioning the apparatus to execute target system program instructions in accordance with the structural characteristics of the target system for which the program was originated.

Abstract: A device controller having a microprogrammed control store for storing instructions useable in the control of the controller and a scratch pad memory for storing device specific information useable in the control and operation of the device is provided. An addressed instruction is received by an instruction register from which control signals are generated. The contents of the instruction register are used to address the control store as well as the scratch pad memory and in addition is received by means of a multiplexor by an arithmetic unit which provides computations in the controller. The multiplexor which in addition receives signals from the scratch pad memory and the devices is also directly coupled to write information in the scratch pad memory. The controller may receive diagnostic and other instructions from a coupled data processor which are then used to control the operation of the controller in place of the instructions in the control store.

Abstract: A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.