Abstract: A covered enclosure surface sensing device, with an on-chip 2-D phased array radar sensor, beam-steering to create a three-dimensional image of the enclosure's interior. An environmental encasing contains a processor, a motion detector, a communication module coupled to an external communication antenna, a power source. It is attachable to a lid or upper side surface of the enclosure. After scanning, the device measures positions of, if present, flexible surfaces and obstructions within the enclosure and a level of liquid or powder in the bottom of the enclosure. If the enclosure contains an open channeled inlet and outlet, it measures liquid levels in the inlet and outlet, the position of the inlet and outlet, and the speed of fluid in the inlet and outlet. If the motion detector detects a threshold movement of the lid or surface sensing device, the phased array radar sensor performs a reorientation scan.

Abstract: An environmental sensor device with a sensor enclosure is configured for use in a gas environment. An enclosure support, at least one sensor on a face of the enclosure; and at least one debris sloughing structure is used. The debris sloughing structure is composed of a channel with a set of inner and outer ridges disposed in the enclosure around a periphery of the at least one sensor, wherein a top portion of the debris sloughing structure above the at least one sensor and lateral portions of the debris sloughing structure on lateral sides of the at least one sensor. A shape and arrangement of the debris sloughing structure carries condensate or contaminants forming on non-sensor areas of the enclosure away from the sensor and to a bottom portion of the enclosure.

Abstract: A combined sewer/enclosure overflow (CSO) sensor system is described for accurate detection and measurement of overflow events. From the combined data, trending information can determine if there is debris accumulation. Rain masks can be used in the trending data to measure overall health. External sensors in combination with the CSO sensors provide predictive information and additional levels of information/data accuracy. The sensor system automatically and remotely monitors CSO locations and provides real-time data regarding start times, stop times, duration, and flow volumes of overflows that occur in these structures and provide regulatory and public notification of these events.

Abstract: A combined sewer/enclosure overflow (CSO) sensor system is described for accurate detection and measurement of overflow events. From the combined data, trending information can determine if there is debris accumulation. Rain masks can be used in the trending data to measure overall health. External sensors in combination with the CSO sensors provide predictive information and additional levels of information/data accuracy. The sensor system automatically and remotely monitors CSO locations and provides real-time data regarding start times, stop times, duration, and flow volumes of overflows that occur in these structures and provide regulatory and public notification of these events.

Abstract: A covered enclosure surface sensing device, with an on-chip 2-D phased array radar sensor, beam-steering to create a three-dimensional image of the enclosure's interior. An environmental encasing contains a processor, a motion detector, a communication module coupled to an external communication antenna, a power source. It is attachable to a lid or upper side surface of the enclosure. After scanning, the device measures positions of, if present, flexible surfaces and obstructions within the enclosure and a level of liquid or powder in the bottom of the enclosure. If the enclosure contains an open channeled inlet and outlet, it measures liquid levels in the inlet and outlet, the position of the inlet and outlet, and the speed of fluid in the inlet and outlet. If the motion detector detects a threshold movement of the lid or surface sensing device, the phased array radar sensor performs a reorientation scan.

Abstract: A combined sewer/enclosure overflow (CSO) sensor system is described for accurate detection and measurement of overflow events. From the combined data, trending information can determine if there is debris accumulation. Rain masks can be used in the trending data to measure overall health. External sensors in combination with the CSO sensors provide predictive information and additional levels of information/data accuracy. The sensor system automatically and remotely monitors CSO locations and provides real-time data regarding start times, stop times, duration, and flow volumes of overflows that occur in these structures and provide regulatory and public notification of these events.

Abstract: An environmental sensor device with a sensor enclosure is configured for use in a gas environment. An enclosure support, at least one sensor on a face of the enclosure; and at least one debris sloughing structure is used. The debris sloughing structure is composed of a channel with a set of inner and outer ridges disposed in the enclosure around a periphery of the at least one sensor, wherein a top portion of the debris sloughing structure above the at least one sensor and lateral portions of the debris sloughing structure on lateral sides of the at least one sensor. A shape and arrangement of the debris sloughing structure carries condensate or contaminants forming on non-sensor areas of the enclosure away from the sensor and to a bottom portion of the enclosure.

Abstract: A combined sewer/enclosure overflow (CSO) sensor system is described for accurate detection and measurement of overflow events. From the combined data, trending information can determine if there is debris accumulation. Rain masks can be used in the trending data to measure overall health. External sensors in combination with the CSO sensors provide predictive information and additional levels of information/data accuracy. The sensor system automatically and remotely monitors CSO locations and provides real-time data regarding start times, stop times, duration, and flow volumes of overflows that occur in these structures and provide regulatory and public notification of these events.

Abstract: A combined sewer/enclosure overflow (CSO) sensor system is described for accurate detection and measurement of overflow events. From the combined data, trending information can determine if there is debris accumulation. Rain masks can be used in the trending data to measure overall health. External sensors in combination with the CSO sensors provide predictive information and additional levels of information/data accuracy. The sensor system automatically and remotely monitors CSO locations and provides real-time data regarding start times, stop times, duration, and flow volumes of overflows that occur in these structures and provide regulatory and public notification of these events.

Abstract: A combined sewer/enclosure overflow (CSO) sensor system is described for accurate detection and measurement of overflow events. From the combined data, trending information can determine if there is debris accumulation. Rain masks can be used in the trending data to measure overall health. External sensors in combination with the CSO sensors provide predictive information and additional levels of information/data accuracy. The sensor system automatically and remotely monitors CSO locations and provides real-time data regarding start times, stop times, duration, and flow volumes of overflows that occur in these structures and provide regulatory and public notification of these events.

Abstract: An integrated circuit or chip having a number of bond pads or inputs that may or may not have a bond wire connecting the pad to a supply voltage, ground or via a package pin to an external input when the chip is placed in the package. The circuits such as the input buffer connected to the pad are normally biased in the opposite voltage to that which the bond wire may be connected. For example, the input buffer circuitry connected to the bond pad, may see the pad as being connected to ground if the bond wires are connected, otherwise the input buffer circuitry will see the pad as being connected to VCC. When the pad is connected to a package pin then the end user may apply an electrical signal (e.g., supply voltage or ground) so that the integrated circuit may be configured as any one of a number of possible devices having one of a set of electrical attributes. Typically, the chip will have up to 8 such pads which can be used individually or in combination to configure the device.

Abstract: An integrated circuit or chip having a number of bond pads or inputs that may or may not have a bond wire connecting the pad to a supply voltage, ground or via a package pin to an external input when the chip is placed in the package. The circuits such as the input buffer connected to the pad are normally biased in the opposite voltage to that which the bond wire may be connected. For example, the input buffer circuitry connected to the bond pad, may see the pad as being connected to ground if the bond wires are connected, otherwise the input buffer circuitry will see the pad as being connected to VCC. When the pad is connected to a package pin then the end user may apply an electrical signal (e.g., supply voltage or ground) so that the integrated circuit may be configured as any one of a number of possible devices having one of a set of electrical attributes. Typically, the chip will have up to 8 such pads which can be used individually or in combination to configure the device.

Abstract: An output buffer includes a continuously variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as a pullup/pulldown transistor, for receiving an input signal and generating an output signal on an output node in response thereto. In addition, the buffer includes a control circuit and a low-impedance driver in an electrical communication with the output node and, preferably, disposed in parallel with at least one of the pullup and/or pulldown transistors. The control circuit receives the output node voltage and generates a control signal on a control node that varies according to the magnitude of the output node voltage. The driver is biased by the control signal and has a conductivity that varies according to the control signal. The variations in the conductivity are operative to adjust the output impedance of the buffer.

Abstract: The present invention concerns an output buffer, which overcomes previous disadvantages of driving transmission line loads by providing a variable output impedance in response to the load on the output. The buffer generally comprises a pullup device for providing a high voltage at the output in response to a first input, a pulldown device configured to provide a low voltage at the output in response to a second input and a second pulldown device configured to provide additional low drive at the output. The second pulldown device provides an impedance at the output which varies with respect to the voltage present at the output.

Abstract: An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and disposed between first and second capacitor terminals. A non-overlapping signal generator is formed from a pair of NOR gates, and an inverter, to generate a pair of control signals CS1, and CS2 wherein when one of the control signals is active, the other control signal is inactive. Four n-channel transistors are provided in a switching matrix. One pair of the four n-channel transistors responds to control signal CS2 to connect the capacitor formed by the n-channel transistor across and between ground, and the output pad. In this switched configuration, a voltage level on the output pad is effectively impressed upon the capacitor, and is stored thereon.

Abstract: An improved I/O cell is disclosed which includes a combined p-channel and n-channel transistor pullup configuration. In particular, such combination is connected in series between the chip operating voltage V.sub.cc, and the I/O cell output pad. The n-channel transistor is biased substantially continuously on its gate terminal with a pumped voltage from a charge pump, which permits it to pass voltages up to and including V.sub.cc. The p-channel transistor operates in its normal fashion, controllable via a pullup select signal applied to its gate terminal to pull the pad high. During normal operation, the n-channel transistor is always ON, thus reducing the substantial dynamic current drawn from the charge pump. The voltage appearing on the pad is fed back to a second n-channel transistor. When the voltage on the pad exceeds V.sub.cc for example, a 5 volt signal when V.sub.cc is 3.

Abstract: A method and apparatus to eliminate the problem of requiring sizing of the row and column decoders according to the pitch of the cells in the memory array is to decouple the decoder cell pitch from the memory cell pitch without causing the chip area to increase dramatically. Decoupling is accomplished by driving the array from both sides for row drivers and by driving the array from both the top and bottom for column drivers. This is achieved in one embodiment by driving alternating rows from opposite sides for row decoders. Even numbered rows are driven from one side and odd numbered rows are driven from the other side. Alternating columns are driven from both the top and bottom. For example, odd numbered columns are driven from the top while even numbered columns are driven from the bottom. In a second embodiment, predetermined rows are driven from one side while the others are driven from the other side.

Abstract: An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance C.sub.gs of the pullup transistor is used to self-bootstrap the input data signal. A pass n-channel transistor is connected between the input data signal, and the gate of the pullup transistor, and is biased on a gate terminal thereof by a charge pump having a voltage magnitude one device threshold higher than the device operating rail V.sub.cc. The pass transistor, so biased, permits the input data signal, which may have a magnitude of V.sub.cc, to charge C.sub.gs. An over-voltage can be developed on the gate of the pullup transistor by the self-bootstrapping effect of C.sub.gs. The pass transistor, in addition, so biased, prevents such over-voltage on the pullup transistors gate from being shorted to V.sub.cc through a driving device.

Abstract: A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2, involves controlling the voltage V1 on gate of MN1 using a gate node N1 that is coupled to supply voltage VCC under the control of two transistor pairs MN3, MN4 and MP3, MP4 that sense the voltages on IO1 and IO2, and an inverter pair MP2, MN2 having a voltage signal ENB input on its gates. If the voltages on nodes IO1 and IO2 both go high, MP3 and MP4 tend to turn OFF dropping gate voltage V1, via MP2, below VCC and tending to turn MN1 OFF. Leakage from node N1 in such event occurs through a small current bleed network formed by three transistors MN6, MN7, and MN8.

Abstract: Synchronous array logic circuitry and a system for automatically laying out such circuitry for the fabrication of integrated circuits are described. The synchronous array logic circuitry includes as many cells as necessary to perform the desired functions with each cell including a transistor array for evaluating a Boolean function and supplying the result to a storage element through a multiplexer. The storage element latches the output signal and supplies it to other transistor arrays and/or other cells. The transistor array includes serially connected transistors for performing AND functions and parallel connected transistors for performing OR functions. The multiplexer operates under control of a test signal to configure the storage elements serially, thereby enabling complete testability of all cells.