Patents by Inventor David B. Rhine

David B. Rhine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9701119
    Abstract: A fluid ejection chip and associated methods of forming are disclosed. According to an exemplary embodiment, the fluid ejection chip comprises a substrate, a flow feature layer, and a nozzle layer. The flow feature layer is disposed over the substrate and has an exposed hydrophilic surface layer with an ink contact angle of about 80 degrees. The nozzle layer is disposed over the flow feature layer and has a thickness of about 4 microns to about 8 microns and an exposed hydrophobic surface layer having an ink contact angle of about 115 degrees.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: July 11, 2017
    Assignee: Funai Electric Co., Ltd.
    Inventors: David C. Graham, David B. Rhine, Sean T. Weaver, Christopher A. Craft
  • Publication number: 20150360466
    Abstract: A fluid ejection chip and associated methods of forming are disclosed. According to an exemplary embodiment, the fluid ejection chip comprises a substrate, a flow feature layer, and a nozzle layer. The flow feature layer is disposed over the substrate and has an exposed hydrophilic surface layer with an ink contact angle of about 80 degrees. The nozzle layer is disposed over the flow feature layer and has a thickness of about 4 microns to about 8 microns and an exposed hydrophobic surface layer having an ink contact angle of about 115 degrees.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: David C. Graham, David B. Rhine, Sean T. Weaver, Christopher A. Craft
  • Patent number: 7344994
    Abstract: A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop material. The first layer is a relatively soft etch stop material. A second layer is applied to the first layer on the back side of the substrate to provide a composite etch stop layer. The second layer is a relatively hard etch stop material. The substrate is etched from a side opposite the back side of the substrate to provide a slot in the substrate.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: March 18, 2008
    Assignee: Lexmark International, Inc.
    Inventors: John W. Krawczyk, Andrew L. McNees, Christopher J. Money, Girish S. Patil, David B. Rhine, Karthik Vaideeswaran
  • Patent number: 6793462
    Abstract: A fluidic pump (108) comprises an electrolyte cavity (110) and a pump outlet (115) fluidically coupled to the electrolyte cavity that are within at least a portion of a fluid guiding structure (105), two electrodes (112, 113) extending from the fluid guiding structure into the electrolyte cavity; and a vapor permeable membrane (120) that prevents an electrolyte (125) in the electrolyte cavity from passing through the pump outlet while allowing gas to flow through the pump outlet.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: September 21, 2004
    Assignee: Motorola, Inc.
    Inventors: Thomas J. Smekal, Piotr Grodzinski, David B. Rhine
  • Patent number: 6787339
    Abstract: The present invention provides low cost microfluidic devices having embedded metal conductors. The devices of the invention comprise a electronic component comprising a substrate having a first surface, a layer of electrically-conductive material deposited on a portion of the first substrate surface, a first sublayer of electrically-insulating material deposited on the first substrate surface and on the layer of electrically-conductive material, a second sublayer of electrically-insulating material deposited on the first sublayer of insulating material, and a third sublayer of electrically-insulating material deposited on the layer of dielectric material, and a fluid-handling component having a contoured surface affixed to the electronic component. The devices of the invention are advantageously used for performing electric field lysis and the polymerase chain reaction. The invention further advantageously provides simple, low cost methods for fabricating such microfluidic devices.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: September 7, 2004
    Assignee: Motorola, Inc.
    Inventors: David B. Rhine, Thomas J. Smekal
  • Publication number: 20040018095
    Abstract: A fluidic pump (108) comprises an electrolyte cavity (110) and a pump outlet (115) fluidically coupled to the electrolyte cavity that are within at least a portion of a fluid guiding structure (105), two electrodes (112, 113) extending from the fluid guiding structure into the electrolyte cavity; and a vapor permeable membrane (120) that prevents an electrolyte (125) in the electrolyte cavity from passing through the pump outlet while allowing gas to flow through the pump outlet.
    Type: Application
    Filed: July 25, 2002
    Publication date: January 29, 2004
    Inventors: Thomas J. Smekal, Piotr Grodzinski, David B. Rhine
  • Patent number: 5051811
    Abstract: A method of preparing a substrate such as a semiconductor chip or ceramic thin film having vias for soldering to a substrate requires that a first metal that is resistive to solder bonding be deposited on the backside of the semiconductor device. The deposited metal is removed from the surface of the semiconductor device, leaving the vias of the semiconductor device having the first metal deposited through them. This technique is useful in any requirement requiring a solder or brazing barrier. This is, a photolithographic process in conjunction with a refractory or nonsolderable metal deposit is used to achieve an alloy or solder barrier.
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: September 24, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Ralph E. Williams, David B. Rhine, John Bedinger, Larry G. Barnett
  • Patent number: 4827610
    Abstract: A method of preparing a substrate such as a semiconductor chip or ceramic thin film having vias for soldering to a substrate requires that a first metal that is resistive to solder bonding be deposited on the backside of the semiconductor device. The deposited metal is removed from the surface of the semiconductor device, leaving the vias of the semiconductor device having the first metal deposited through them. This technique is useful in any requirement requiring a solder or brazing barrier. That is a photolithographic process in conjunction with a refractory or nonsolderable metal deposit is used to achieve an alloy or solder barrier.
    Type: Grant
    Filed: August 31, 1987
    Date of Patent: May 9, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Ralph E. Williams, David B. Rhine, John Bedinger, Larry G. Barnett