Abstract: A direct-digital synthesizer for generating a waveform includes a digital accumulator fed by a phase increment word and a series of clock pulses for successively adding the phase increment word to produce a series of N bit phase words. A table or trigonometric engine produces sine and cosine digital signals related to the M most significant bits of the phase word produced by the accumulator. A feedback loop is fed by truncation error words comprising at least a portion of N-M least significant bits of the N bit phase words producing truncation error compensation words. The feedback loop includes a digital filter. The feedback loop includes a digital filter. The feedback loop including the digital filter provides a low pass truncation error response to the truncation error having at least one zero in the transfer function thereof at DC.

Abstract: An asymmetrical modem system wherein a modem at a first location transmits information to a modem at a second location on a downstream signal and the modem at the second location transmits information to the modem at the first location on an upstream signal. The system includes a first location transmitter section, having an N-point inverse frequency transform, for converting information into the downstream signal having up to (N/2)-1 carriers. A second location transmitter section having, an [(NL)/(2K)-point inverse frequency transform, converts information into the upstream analog signal having up to [(NL)/(2K)]-1 carriers, where K is the ratio of downstream signal bandwidth to upstream signal bandwidth and L is greater one. A receiver section at the first location, having an [NM/K]-point frequency transform, separates the upstream signal into up to [(NM)/(2K)]-1 upstream carriers, where M is greater than one.

Abstract: A method and apparatus for operating an asymmetric digital subscriber loop modem system. A modem at a central office transmits information to a modem at a remote terminal on a down-stream signal having a predetermined bandwidth and the modem at the remote terminal transmits information to the modem at the central office on an up-stream signal having a bandwidth lower than the predetermined bandwidth of the down-stream signal. Digital samples of the up-stream signal in the central office modem are produced. Digital samples representative of an estimated echo signal in the central office modem are also produced. The digital samples of the up-stream signal and the digital samples representative of an estimated echo signal are both fed to a subtractor at the same rate. In a preferred embodiment, the up-stream signal is oversampled (i.e., is sampled at a rate greater than the Nyquist sampling rate) in producing the digital samples thereof. Samples of the down-stream signal are fed to an echo cancellation filter.

Abstract: A data transmission system including a telephone service subscriber loop utilized for transmission of data including telephone service signals; a splitter operable for splitting the subscriber loop into a first transmission path including a low pass filter which accommodates a continuation of telephone service signal transmissions along the subscriber loop and a second transmission path, said second transmission path including a capacitive element for attenuating the telephone service signals; and a digital subscriber loop transceiver coupled to the second transmission path for implementing high rate digital data transmission over the subscriber loop, the transceiver including a frontend processing circuit having a transmit path and a receive path, at least said receive path comprising a high pass filter for further attenuating said telephone service signals.

Abstract: A dual mode ultrasonic imager system operative in both a two dimensional 2-D) mode and doppler mode, includes a plurality of transducers for receiving analog ultrasonic signals and converting them to analog electrical signals, and an analog to digital (A/D) converter system for converting the analog electrical signals to digital signals for further processing. The A/D converter system includes a digital to analog (D/A) converter for converting the digital signals into analog feedback signals, and an analog summer for receiving the analog electrical signals and combining them with the analog feedback signals. An integrator is selectively coupled to receive an output signal from the analog summer and to generate an integrated analog signal. An A/D converter selectively receives, and converts to an equivalent digital signal, one of the integrated analog signal and an output signal of the analog summer.

Abstract: An architecture for oversampled delta-sigma (.DELTA.--.SIGMA.) analog-to-digital (A/D) conversion of high-frequency, narrow-band signals includes multistage .DELTA.--.SIGMA. modulators that incorporate band-reject noise shaping centered at an arbitrary center frequency F.sub.bp. These modulators cascaded with a bandpass digital filter centered at the arbitrary center frequency F.sub.bp perform A/D conversion for high-frequency, narrow-band signals having the same arbitrary frequency. The bandpass modulators are implemented by use of resonators which provide a substantially large gain at the arbitrary frequency.

Abstract: A computerized tomography system includes a detector array made up of a set of detector subelements aligned along a slice thickness direction. A controllable switching matrix selectively interconnects a predetermined number of successive detector subelements to a respective summing amplifier to produce slice-constituent signals which measure a respective slice positioned to pass through a body. Each respective slice having a selectable thickness in a region of interest to be imaged.

Abstract: A sampled signal integrator is provided comprising: an amplifier; two pairs of capacitors, the first pair of capacitors being coupled between the input and output terminals of the amplifier in a conventional negative feedback configuration, and the second pair of capacitors being coupled to the input terminals of the amplifier by a first pair of switches and likewise being coupled to a Voltage source by a second pair of switches; the two pairs of switches being further cross-coupled or synchronized to accomplish double-rate integration; and a voltage bias coupled in shunt with each of the input terminals of the amplifier to thereby provide a common mode bias to the integrator. Likewise, in another embodiment of the invention, the output signals of a sampled signal integrator configured so as to accomplish double-rate integration may be modulated and decimated to reduce or remove DC or low frequency noise.

Abstract: A combined programmable gain and integrating amplifier comprises an operational amplifier having an inverting input terminal coupled to a reference voltage. A plurality of capacitors are selectively connectable in parallel between the inverting input terminal and the amplifier output terminal. At least one terminal of each capacitor is connected to the inverting input terminal. A plurality of controllable switches are connected in series circuit between a corresponding one of the capacitors and the amplifier output terminal for coupling the capacitors in circuit between the inverting input terminal and the output terminal. In a first operational state, each of the switches connects the capacitors between the input and output terminals. In a second operational state, the switches connect selected ones of the capacitors the reference voltage.

Abstract: An architecture for oversampled delta-sigma (.DELTA.-.SIGMA.) analog-to-digital (A/D) conversion of high-frequency, narrow-band signals includes multistage .DELTA.-.SIGMA. modulators that incorporate band-reject noise shaping centered at one fourth the clock frequency Fs. These modulators cascaded with a bandpass digital filter also centered at a frequency of Fs/4 perform A/D conversion for high-frequency, narrow-band signals centered at the same frequency. The bandpass modulators are implemented by use of resonators in existing low-pass multistage modulators.

Abstract: A high-order sigma-delta modulator has a single feedback loop including a linear network and a quantizer, which quantizer comprises a plural-bit analog-to-digital converter, a digital comparator and a single-bit digital-to-analog converter. The linear network comprises a cascade of integrators, a second-order resonator, a cascade of second-order resonators or a cascade of second-order resonators with an additional integrator. The loop behaves much the same as a conventional single-feedback-loop, one-bit sigma-delta modulator, inasfar as the feedback signal is concerned. However, a plural-bit preliminary output signal is available, so the truncation error can be determined.

Abstract: An improved modulator network for an interpolative oversampled (sigma-delta) analog-to-digital converter comprises a second-order modulator, which performs double integration of error between its digital output signal and its analog input signal, and a first-order modulator, which performs single integration of error between its digital output signal and an analog signal supplied thereto from the second-order modulator. The modulators supply their output signals to a digital error cancellation circuit which suppresses in the signal supplied to a decimation filter the quantization noise arising in the second-order modulator. The network exhibits significantly reduced sensitivity to the practical nonidealities that normally limit the resolution of analog-to-digital converters of this type, i.e., component matching, amplifier nonlinearity, finite gain, settling time, and signal dynamic range.

Abstract: In an oversampling interpolative analog-to-digital converter having a sigma-delta modulator followed in cascade by a decimation filter, the decimation filter supplies digital output signals for the oversampling analog-to-digital converter at an output rate that is a submultiple 1/R of an oversampling rate at which digital samples of an input signal for said decimation filter are supplied. The chopping rate of the chopper-stabilized amplifier is a multiple of the output sample rate of the decimation filter to place the fundamental and the harmonics of the chopping at the frequencies corresponding to the zeroes in the decimation filter response, better to keep remnants of the chopper stabilization from appearing in the output samples from the decimation filter.

Abstract: Sigma-delta analog-to-digital conversion is used in sensing apparatus that generates a digital signal descriptive of light energy received by a photosensor, such as one of a plurality of photosensors that together receive various elements of a radiant-energy image. A preamplifier generates an analog output signal responsive to the photocurrent of the photosensor, which analog output signal is undesirably accompanied by wideband noise. The analog output signal is supplied to a sigma-delta analog-to-digital converter, the decimation filter of which not only suppresses in the digital signal a component arising from the quantization noise from the sigma-delta modulator portion of the analog-to-digital converter, but also suppresses a component arising from remnant wideband noise from the preamplifier.

Abstract: An oversampling converter of a type using a plural-order, plural-stage sigma-delta modulator, the output signal to the decimating filter of which modulator has the quantization noise contribution of a number of its plurality of stages suppressed therein, uses single-bit quantization in those stages to help avoid problems of nonlinearity. Each other sigma-delta converter stage, the quantization noise of which appears in substantial amount in the converter output signal to the decimating filter, uses quantization having multiple-bit resolution to help increase the resolution of the oversampling converter overall.

Abstract: An oversampling converter of a type using a plural-order, plural-stage sigma-delta modulator, the output signal to the decimating filter of which modulator has the quantization noise contribution of a number of its plurality of stages suppressed therein, uses single-bit quantization in those stages, and the modulator uses single-bit quantization in those stages. Those stages each employ digital-to-analog converters with single-bit resolution in their feedback connections to avoid non-linearity problems. Another sigma-delta converter stage, the quantization noise of which appears in substantial amount in the converter output signal to the decimating filter, uses quantization having multiple-bit resolution to help increase the resolution of the oversampling converter overall.

Abstract: A preamplifier interfaces low level current-mode signals, such as from a photodetector in a computerized tomography system, to a corresponding voltage-mode signals, with a dynamic range on the order of 120 dB. The preamplifier can be implemented in CMOS technology to allow for complete integration of the computerized tomography interface function, including analog-to-digital conversion, of several channels in a single integrated circuit. The CMOS circuit accepts a current signal at its input and, after integration of the signal, produces a voltage output wherein the low frequency noise that is normally encountered with MOS transistors is cancelled through the use of correlated-double sampling. The circuit limits high frequency noise through use of low-pass filtering.

Abstract: An improved high order interpolative oversampled (sigma delta) analog-to-digital converter network including a plurality of cascade-coupled integrator stages is formed on a single integrated circuit chip in a manner that conserves power and chip area. Each integrator stage includes a differential amplifier, at least one input capacitor and at least one feedback capacitor. The power dissipation and occupied chip area are minimized by down-sizing the chip area occupied by the capacitors and differential amplifiers (op amps) in all but the first integrator stage. The high gain of the first integrator stage makes the noise contribution of subsequent integrator stages negligible so that the higher noise of the subsequent integrator stages is tolerable.

Abstract: A general architecture to correct conversion errors of a multi-stage, pipelined subranging analog-to-digital (A/D) converter includes cascaded stages, each stage generating a binary conversion signal representing the nearest quantized level below that of the analog input signal and a residual analog signal applied to the next conversion stage. The binary conversion signal from each stage addresses individual or common look-up tables providing a compensated binary signal selected to compensate for nonidealities of the A/D converter components. The compensated binary signals from the look-up tables provide a corrected output signal when summed together. A simple method of calibration for the A/D converter makes use of a least-mean-squared adaptation algorithm. The A/D converter accommodates practical circuit nonidealities such as component mismatching, gain error and voltage offsets, and handles high levels of amplifier nonlinearity.

Abstract: A circuit transformation that doubles the effective sampling rate of any switched capacitor oversampled, interpolative modulator, regardless of its order, employs, in each integrator of the modulator, a second input capacitor and switches that operate on alternate clock phases. In addition, two quantizers, instead of one, are employed in the network and are operated on opposite clock phases. Alternatively, the quantizers can be operated at twice the normal rate if feasible for the particular circuit. The effective operating rate is thereby doubled without any increase in clock rate or circuit speed requirements, resulting in improved analog-to-digital resolution or conversion rate.