Abstract: A method and apparatus for passing messages between nodes in a distributed network of interconnected nodes wherein a two dimensional array is arranged with each of the nodes represented by a single row heading and a single column heading. The intersections of row and column headings between which messages are to pass may be provided with a token indicative of this condition. The token may further be associated with message parameters defining the passage of the message and operations to be performed thereon, between the two nodes represented by the intersecting row and column headings. Successive versions of the two dimensional array may be provided to form a three dimensional array for passing messages between nodes over the network via successive communication patterns defined by the successive versions of the two dimensional array.

Abstract: A method and apparatus for passing messages between nodes in a distributed network of interconnected nodes wherein a two dimensional array is arranged with each of the nodes represented by a single row heading and a single column heading. The intersections of row and column headings between which messages are to pass may be provided with a token indicative of this condition. The token may further be associated with message parameters defining the passage of the message and operations to be performed thereon, between the two nodes represented by the intersecting row and column headings. Successive versions of the two dimensional array may be provided to form a three dimensional array for passing messages between nodes over the network via successive communication patterns defined by the successive versions of the two dimensional array.

Abstract: A method and apparatus for performing operations at nodes in a distributed network of interconnected nodes wherein a two dimensional array is arranged with each of the nodes represented by a single row heading and a single column heading. The intersections of row and column headings at which operations are to be performed may be provided with a token indicative of this condition. The token may further be associated with operation parameters defining the performance of the operations at the two nodes represented by the intersecting row and column headings.

Abstract: A method and apparatus for performing operations at nodes in a distributed network of interconnected nodes wherein a two dimensional array is arranged with each of the nodes represented by a single row heading and a single column heading. The intersections of row and column headings at which operations are to be performed may be provided with a token indicative of this condition. The token may further be associated with operation parameters defining the performance of the operations at the two nodes represented by the intersecting row and column headings.

Abstract: A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge.

Abstract: A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their memory providing the network routing and shared memory. Each of the nodes provides a functional unit with a processor, shared memory, and communication interface. K zipper ports in addition provide a switching function to interconnect the distributed memory and processors providing the shared memory. The resulting multi-ported shared intelligent memory switch can be used to connect (switch) a variety of computer system elements (CSEs) including computers and direct access storage devices (DASDs). The multi-ported intelligent memory shared memory organized into a collection of cells or nodes and is called the hedgehog. Each node comprises a finite computer memory, a processing unit, and communication interface and at least K of the nodes of the device have a zipper port.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Abstract: The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Abstract: The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Abstract: An architecture uses a process, termed "encapsulation", by which queues and counters are only accessed through a special memory operand called "object storage". The system alone is in control of the object storage, and the user cannot access it directly at any time. If the user needs to access a queue, the user must request it from the system. The system will in turn provide such access by issuing the user a "token". This token is the only means of communication between the user and the requested queue. By providing threads to be dispatched to real processors without large operating overhead, through object storage, the operating systems do not need to wait for the system's dispatching process to complete. Operating systems can signal the system through the use of object storage that they are authorized to access the processor when needed and thus forego the long dispatching process. In addition, since real processors are not dedicated, they can execute other programs when not needed.

Abstract: Computer elements in a massively parallel computer system are interconnected in such a way that the number of connections per element can be balanced against the network diameter or worst case path length. This is done by creating a topology that maintains topological properties of hypercubes yet improves flexibility by enumerating the nodes of the network in number systems whose base can be varied. Topologies are generated in which nodes are not always connected when their addresses differ in a single digit. A new variable d is introduced, the purpose of which is to control the overall density of the network by controlling the number of intermediate arc connections within the rings of the network.