Abstract: A processing system is configured for providing an external in circuit emulator with an internal execution state resulting from the execution by a first processor of an internal instruction stored in an internal instruction cache. The processing system includes a second processor which includes an internal instruction cache for also storing the internal instructions. The second processor is coupled to the first processor in a master/slave configuration to enable the second processor to duplicate the instruction executions of the first processor. The second processor includes an output for providing the internal execution state which is coupled to the in circuit emulator by an external address bus for providing the internal execution parameter to the in circuit emulator.

Abstract: There is disclosed a timing system for use in a microprocessor for initiating microprocessor outputs onto an input sampling from an external bus in synchronism with a bus timing clock. The timing system is operative in a first mode for internally generating the bus timing clock and in a second mode for being driven from an externally generated bus timing clock. In the first mode, the timing system generates first and second inverse phase timing clocks responsive to an external clock source and independently generates the internally generated bus timing clock with the rising edges of the bus timing clock coinciding with the rising edges of the first microprocessor timing clock and the falling edges of the second microprocessor timing clock. In the second mode, the timing system generates the first and second microprocessor timing clocks in response to the externally generated bus timing clock.

Abstract: A processing system provides efficient accessing by a processor of a memory during a sequential memory access. The processing system includes a memory having a plurality of storage locations, each being addressable at a corresponding different storage address, a processor coupled to the memory for addressing the memory storage locations for accessing the storage locations and control means coupled to the memory and to the processor. The control means is responsive to a sequential access by the processor for causing the processor to address selected spaced apart ones of the storage locations in order and is arranged to access the other memory locations in order between the processor addresses to provide an access rate of one word of information per system clock cycle.

Abstract: The system comprises a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on the inputs to produce mimicked outputs, compares the mimicked outputs with the master outputs and indicates an error condition if the mimicked outputs do not equal the master outputs. A checking circuit forces a difference between the mimicked output and the master output and determines if the master slave configuration accurately determines the presence of the forced error.

Abstract: There is disclosed a self-regulating clock generator for providing an output clock signal to clock a CMOS microprocessor. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch arranged to be set and reset by the input clock signal and having an output for providing the output clock signal. A delay circuit is coupled to the latch output and enables the setting and resetting of the latch to establish the phase lengths. Also disclosed is a second clock generator which includes a pair of latches and a pair of delay circuits for providing an output clock signal having first and second phases of different lengths.

Abstract: An integrated electronic circuit is provided comprising: a microprocessor for executing instructions; an instruction cache for storing instructions for execution by the microprocessor, the instruction cache being coupled to the microprocessor for transfer of respective stored instructions to the microprocessor; and circuitry for exchanging respective byte positions of at least two bytes of a respective instruction stored by the instruction cache.

Abstract: A highspeed, intelligent, distributed control memory system is comprised of an array of modular, cascadable, integrated circuit devices, hereinafter referred to as "memory elements." Each memory element is further comprised of storage means, programmable on board processing ("distributed control") means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control.