Abstract: A method, system, apparatus, and architecture are provided for monitoring, handling, and escalating faults from a plurality of SoC subsystems by deploying at least one FCU instance at each SoC subsystem, where each FCU instance is configured to monitor one or more fault input signals at one or more fault inputs, to generate a local control signal for one or more hardware resources controlled by the FCU instance, and to escalate any unresolved fault on a fault output, and where a first plurality of FCU instances deployed at a first plurality of SoC subsystems are each connected in a fault escalation tree with an escalation FCU instance deployed at a first management SoC subsystem by connecting the fault outputs from the first plurality of FCU instances to the one or more escalation fault inputs of the escalation FCU instance deployed at the first management SoC subsystem.

Abstract: A fault reaction handling time interval (FRTI) for a reaction to the fault is determined based on a domain identifier (DID) indicative of an application associated with a fault. A first reaction to recover from the fault is signaled and then a determination is made whether a safe state is reached after the FRTI. Based on the safe state not being reached, a second FRTI is determined for a second escalated reaction, the second FRTI also being based on the DID. Typically, the second reaction results in less system availability so by defining the FRTI based on the DID sufficient time is allowed for reaching a safe state before the reaction is escalated.

Abstract: A processing system, such as for an automobile, includes multiple processor cores, including an application core and a safety core, and a fault detection circuit in communication with the processor cores. The fault detection circuit includes a progress register for storing progress data of an application executed on the application core. The safety core, which executes a fault detection program, reads the progress data from the progress register, and generates an output based on the progress data and an expected behavior of the application. The safety core writes the output to a status register of the fault detection circuit. The fault detection circuit includes a controller that reads the status register and generates a fault signal when the output indicates there is a fault in the execution of the application. In response, the application core either recovers from the fault or runs in a safe mode.

Abstract: A processing system, such as for an automobile, includes multiple processor cores, including an application core and a safety core, and a fault detection circuit in communication with the processor cores. The fault detection circuit includes a progress register for storing progress data of an application executed on the application core. The safety core, which executes a fault detection program, reads the progress data from the progress register, and generates an output based on the progress data and an expected behavior of the application. The safety core writes the output to a status register of the fault detection circuit. The fault detection circuit includes a controller that reads the status register and generates a fault signal when the output indicates there is a fault in the execution of the application. In response, the application core either recovers from the fault or runs in a safe mode.

Abstract: Counter based heartbeat messaging is implemented by storing heartbeat count vectors and health vectors of each core in a shared memory. Each core implements its heartbeat operation by storing the heartbeat count and health vectors from shared to local memory. A core uses its locally stored vectors to detect fault conditions at the other cores, and to achieve interactive consistency. Any core can initiate a system reaction to a core having a failing health status when a defined number of cores agree with that status.

Abstract: A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. The predetermined temporal relationship may require the first state machine to progress to the first state machine state before the progress to the second state. The current state of the temporal relationship state machine may be one of a first temporal relationship state and a second temporal relationship state. The second state may be a second state machine state of the first state machine. The second state may be a second state machine state of a second state machine.

Abstract: Counter based heartbeat messaging is implemented by storing heartbeat count vectors and health vectors of each core in a shared memory. Each core implements its heartbeat operation by storing the heartbeat count and health vectors from shared to local memory. A core uses its locally stored vectors to detect fault conditions at the other cores, and to achieve interactive consistency. Any core can initiate a system reaction to a core having a failing health status when a defined number of cores agree with that status.

Abstract: An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.

Abstract: A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. The predetermined temporal relationship may require the first state machine to progress to the first state machine state before the progress to the second state. The current state of the temporal relationship state machine may be one of a first temporal relationship state and a second temporal relationship state. The second state may be a second state machine state of the first state machine. The second state may be a second state machine state of a second state machine.

Abstract: A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts for control flow paths through the computer program code, and inserting at least one probe within the computer program code to enable a cumulative instruction count value for at least one control flow path of the computer program code to be accessed.

Abstract: An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.

Abstract: A method of developing a tracing solution for the execution of blocks of computer code. The method comprises representing each block of code of an initial tracing solution as a vertex on an initial tracing solution graph. The vertices on the initial tracing solution graph constitute an initial set of vertices. The method further comprises checking whether there are any redundant vertices in the initial set of vertices. Redundant vertices are vertices not needed for a tracing solution. If there are any redundant vertices in the initial set of vertices, one or more of the redundant vertices is eliminated from the initial set of vertices, thereby deriving a reduced set of vertices.

Abstract: A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts for control flow paths through the computer program code, and inserting at least one probe within the computer program code to enable a cumulative instruction count value for at least one control flow path of the computer program code to be accessed.

Abstract: A method of developing a tracing solution for the execution of blocks of computer code. The method comprises representing each block of code of an initial tracing solution as a vertex on an initial tracing solution graph. The vertices on the initial tracing solution graph constitute an initial set of vertices The method further comprises checking whether there are any redundant vertices in the initial set of vertices. Redundant vertices are vertices not needed for a tracing solution. If there are any redundant vertices in the initial set of vertices, one ore more of the redundant vertices is eliminated from the initial set of vertices, thereby deriving a reduced set of vertices.