Abstract: A controller includes a volatile random access memory and translation hardware. The volatile random access memory includes a table having at least one entry. The at least one entry includes a portion of a physical address of a memory location at a NAND flash non-volatile solid-state memory. The volatile random access memory is accessible to the translation hardware. The translation hardware is configured to sum binary data bits of a portion of a logical address and a pointer value to determine a random access memory address of the at least one entry and is configured to determine the portion of the physical address of the memory location at the NAND flash non-volatile solid-state memory based at least in part on the random access memory address of the at least one entry.

Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.

Abstract: A system and method for providing direct memory access is disclosed. In a particular embodiment, a direct memory access module is disclosed that includes a memory, a first interface coupled to a processor, and a second interface coupled to a peripheral module. A first instruction received from the first interface is stored in the memory. The first instruction includes a number of programmed input/output words to be provided to the peripheral module via the second interface. The direct memory access module also includes an instruction execution unit to process the first instruction.

Abstract: A method of executing a program using a processor is implemented by executing a first main program segment stored in a ROM device until a first ROM instruction address, corresponding to one of a first sequence of ROM instructions, matches one of a plurality of a patch addresses stored in a patch register set. In response to this matching, a first patch program segment, stored in a RAM device, is executed.

Abstract: Disclosed is a system and method for widening base linear chirp signals from a first bandwidth to a larger second bandwidth while controlling the proliferation of spurious (unwanted) signals. One aspect of the invention provides for using a phase locked loop (PLL) for generating an output signal having a greater bandwidth than the bandwidth associated with the chirp signal. The PLL effectively tracks a reference signal generated at least in part by the chirp source to reduce spurious signals in the output signal. Another aspect of the invention is to use a common local oscillator in the signal transmit and receive paths to cancel consistent phase non-linearity's.

Abstract: A long-life telemetry power storage and delivery system includes a power bus electrically connected through a voltage regulator to a wireless communications unit operable for periodic high-current transmissions. The power bus is connected to a direct power source and at least three power storage sources. The direct power source includes at least one solar panel. The power storage sources include: (1) a primary, low-voltage, non-rechargeable battery; (2) a secondary, low-voltage, rechargeable battery; and (3) a set of high capacity capacitors. To provide a long life to the system, current limiting resistors are interposed between the power bus and the primary and secondary batteries, such that high current requirements of a transmission are supplied by the set of capacitors rather than the batteries.

Abstract: A metadata provision system and method is described. The system comprises a transmitter (30) and a receiver (60). The transmitter (30) is arranged to transmit metadata corresponding to content data. The receiver (60) is arranged to receive the transmitted metadata, wherein the receiver (60) is arranged to store the metadata and output the metadata upon request. Preferably the transmitter (30) and receiver (60) operate under the Digital Audio Broadcasting system.

Abstract: A hydraulic bushing assembly includes an inner tube, an elastomeric bushing disposed around the inner tube, an insert disposed around the elastomeric bushing and an outer tube disposed around the insert. The elastomeric bushing and the insert define a pair of chambers which are connected by a passageway defined by the insert. A pair of intermediate tubes are disposed in the elastomeric bushing at opposite axial ends of the insert.

Abstract: An analog-to-digital converter (ADC) system is disclosed and includes a programmable control register and a plurality of channels, each channel having an associated request bit within the programmable control register. The ADC system also includes a scheduler responsive to the programmable control register, the scheduler comprising logic to monitor a plurality of request bits to detect when any of the request bits are set. A method of scheduling analog-to-digital conversion is disclosed and includes receiving a request to schedule an analog-to-digital conversion for a channel of a plurality of channels. The method also includes scheduling an analog-to-digital conversion in response to receiving the request and performing the analog-to-digital conversion based on the request, where data that indicates the request is stored in a programmable control register.

Abstract: A method for generating labor requirements including the step of providing a plurality of sales models based upon historical data, where each sales model is associated with a store within an enterprise. A sales model is selected and a sales forecast is generated based upon the selection of at least one sales model from the plurality of sales models. Workload standards and labor rates are obtained and a labor forecast for the store is generated based upon the sales forecast, the workload standards and the labor rates. Store level users are able to generate the labor requirements.

Abstract: A multi-source data retrieval system is shown. The system includes a list retriever for retrieving a list of data sources and a graphical user interface for presenting the list of data sources to a user. A fetch manager retrieves information about the data sources and downloads information from the data sources. A data combiner combines the downloaded information into composite data for use by another application.

Abstract: A semiconductor device includes a plurality of laser fuses and each laser fuse represents a bit of data. A first set of the plurality of laser fuses represents a unique identifier that corresponds to the semiconductor device. Also, a second set of the plurality of laser fuses represents error correction coding data that corresponds to the unique identifier. The unique identifier can be a digital rights management identification. Also, the error correction coding data is configured for use by a Reed-Solomon error correcting method to correct the unique identifier. Alternatively, the error correction coding data is configured for use by a cyclic redundancy check method.

Abstract: The disclosure is directed to a device including a memory interface. The memory interface includes a data interface, a first state machine and a second state machine. The first state machine includes a first chip select interface and a first ready/busy interface. The first state machine is configured to select and monitor a first memory device via the first chip select interface and the first ready/busy interface, respectively, when the first memory device is coupled to the data interface. The second state machine includes a second chip select interface and a second ready/busy inter-face. The second state machine is configured to select and monitor a second memory device via the second chip select interface and the second ready/busy interface, respectively, when the second memory device is coupled to the data interface.

Abstract: The disclosure includes a system and method of using a processor and protected memory. In a particular embodiment, the system includes a processor, a volatile memory accessible to the processor, and a first nonvolatile memory accessible to the processor. The first nonvolatile memory includes a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation and a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit. The system includes a second nonvolatile memory including data to be transferred to the volatile memory.

Abstract: A system is disclosed that comprises a processor, a memoryless first level page table addressable by the processor, and a second level page table stored in a memory coupled to the processor. The second level page table is addressable by at least one entry of the first level page table.

Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.

Abstract: Methods and systems are disclosed to convert low temperature thermal energy to electricity. An example apparatus disclosed herein includes an electrical generating unit to receive heat energy to produce electricity, a concentrator including a heat engine, a liquid piston operatively coupled to the heat engine, and a heat pump operatively coupled to the liquid piston, the heat engine adapted to collect thermal energy, and the heat pump operatively coupled to the electrical generating unit to provide heat to the electrical generating unit. The example apparatus disclosed herein also includes a heat engine floating piston disposed in the heat engine, a heat pump floating piston disposed in the heat pump, and wherein the heat engine floating piston and the heat pump floating piston oscillate.

Abstract: A pressure accumulator for valves. The pressure accumulator enables pressure to be limited in a water hydrant due to the freezing of the fluid within the valve chamber. The accumulator includes a polymeric material that is able to compress as pressure within the valve increases. The accumulator can further include an external pressure stem surrounding at least a portion of the length of a valve stem of the valve.

Abstract: Systems, methods, and software for storage and distribution of real estate related data. Some embodiments include a database of data representing three-dimensional topographic views of geographic areas and a computer system adapted to present a topographic view of a geographic area based on a query by a user for information related to a listing of a property for sale or lease. In some embodiments, properties for sale or lease are plotted and identified within a three-dimensional topographic view providing the searcher a neighborhood view of the area of interest. Users can move around the three-dimensional topographic view as if they are flying overhead.

Abstract: A front end for a glass forming operation including an open channel and at least one burner. The channel surface has at least one burner port and a burner oriented in the burner port at an acute angle relative to the channel surface. The surface may be a top, side or end wall and the burner port is at an acute angle relative to the surface of the wall.