Abstract: Methods of reducing the viability of cancer cells, preventing cancer cells of a subject from developing resistance to TTFields, and restoring sensitivity of cancer cells to TTFields by recommending or prescribing a PTGER3 inhibitor to a subject and applying an alternating electric field to the cancer cells are provided. In some instances, sensitivity of cancer cells to TTFields can be restored with one or more PTGER3 inhibitors (e.g., NSAIDs, cox2 inhibitors).

Abstract: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first conductive interconnect. Over the first interlevel dielectric layer and the first conductive interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first conductive interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

Abstract: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

Abstract: A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die.

Abstract: A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.

Abstract: Capacitive structures in integrated circuits are disclosed. The capacitive structures are formed on a substrate. Each capacitive structure includes a first conductive finger and a second conductive finger. The first and second conductive fingers are arranged in parallel with each other and separated from each other by a dielectric material. The first finger is connected to a first interconnect and the second conductive finger is connected to a second interconnect. A first capacitor is formed from a first group of the plurality of capacitive structures having respective interconnects coupled together. A second capacitor is formed from a second group of the plurality of capacitive structures having respective interconnects coupled together. The capacitive structures of the first group are intertwined with the capacitive structures of the second group.

Abstract: A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die.

Abstract: Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect and measuring a voltage across the interconnect. The current and voltage may be used to estimate the resistance of the interconnect. The test circuit may charge and discharge the interconnect to estimate the capacitance of the interconnect. The isolation circuits may isolate the pads from the interconnect when the test circuit charges and discharges the interconnect. The apparatus may further include another interconnect, another set of pads, and another set of isolation circuits that may be coupled in a mirror manner. Resistance and/or capacitance mismatch between the two interconnects may be accurately estimated.

Abstract: A configurable ring oscillator is operated in a first configuration so that an oscillating signal passes from a first node to a second node through a first signal path. A first measurement of an operational characteristic is made. The ring oscillator is operated in a second configuration where an oscillating signal passes from the first node to the second node through a second signal path. A second measurement is made. The first and second measurements are used to determine a circuit simulator parameter. If the first path has little interconnect and the second path has substantial interconnect, then the effect on circuit operation due to interconnect loading can be isolated from the effects on circuit operation due to variations in transistor performance. If the first and second paths are laid out to be identical, then the first and second measurements are usable to determine a circuit simulator mismatch parameter.

Abstract: A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.

Abstract: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

Abstract: Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect and measuring a voltage across the interconnect. The current and voltage may be used to estimate the resistance of the interconnect. The test circuit may charge and discharge the interconnect to estimate the capacitance of the interconnect. The isolation circuits may isolate the pads from the interconnect when the test circuit charges and discharges the interconnect. The apparatus may further include another interconnect, another set of pads, and another set of isolation circuits that may be coupled in a mirror manner. Resistance and/or capacitance mismatch between the two interconnects may be accurately estimated.

Abstract: Capacitive structures in integrated circuits are disclosed. The capacitive structures are formed on a substrate. Each capacitive structure includes a first conductive finger and a second conductive finger. The first and second conductive fingers are arranged in parallel with each other and separated from each other by a dielectric material. The first finger is connected to a first interconnect and the second conductive finger is connected to a second interconnect. A first capacitor is formed from a first group of the plurality of capacitive structures having respective interconnects coupled together. A second capacitor is formed from a second group of the plurality of capacitive structures having respective interconnects coupled together. The capacitive structures of the first group are intertwined with the capacitive structures of the second group.

Abstract: A configurable ring oscillator is operated in a first configuration so that an oscillating signal passes from a first node to a second node through a first signal path. A first measurement of an operational characteristic is made. The ring oscillator is operated in a second configuration where an oscillating signal passes from the first node to the second node through a second signal path. A second measurement is made. The first and second measurements are used to determine a circuit simulator parameter. If the first path has little interconnect and the second path has substantial interconnect, then the effect on circuit operation due to interconnect loading can be isolated from the effects on circuit operation due to variations in transistor performance. If the first and second paths are laid out to be identical, then the first and second measurements are usable to determine a circuit simulator mismatch parameter.

Abstract: The claimed universal polymeric molded fire hydrant is lightweight, weather resistant and will meet the UL, FM, NFPA and AWWA standards established for conventional metallic hydrants. Polymeric fire hydrants will also exceed standard performance expectations by eliminating rusting, binding, cracking and the associated need for periodic painting and lubrication. This polymeric fire hydrant costs less to produce than traditional metallic models providing significant costs savings to commercial and residential developers as well as municipalities. The inherent light weight nature of the units will reduce manpower and heavy equipment required to install it. This hydrant can be manufactured to resemble all existing traditional hydrant designs and performance specifications and will allow for future design modifications as future performance specifications and designs evolve.

Abstract: A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

Abstract: A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided.

Abstract: A method of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The method involves forming a metalization pattern using a damascene process which includes forming at least first and second metal regions separated by a dielectric region, forming an air gap at least partially within the dielectric region, and sealing the air gap to entrap the air gap between the first and second metal regions thereby reducing intralevel capacitance between the first and second metal regions.

Abstract: An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first layer of low-k dielectric material overlies the at least one conductive metal line, and a second layer of low-k dielectric material overlies the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured and the second layer of low-k dielectric material is thermally cured.

Abstract: A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.