Abstract: A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

Abstract: An ultra-thin dielectric film is subject to a dynamic electrical bias. During a first phase, the ultra-thin dielectric film is under a high field bias generated by the application of a high voltage. The duration of the high electrical stress is dependent on the intrinsic properties of the ultra-thin dielectric material. In a second phase, the ultra-thin dielectric film is subjected to an operating field bias generated by the application of an operating voltage. The change in the field bias exposes the dielectric to a similar dynamic stress that microelectronic devices ordinarily experience. At the operating field stage, a gate current is measured and compared to a predetermined range. Once the gate current exceeds that range the test concludes. Otherwise, the test cycles between the above-mentioned phases for a predetermined number of iterations based on prior experimental correlation.

Abstract: A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.

Abstract: An interconnect structure capable of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The structure comprises at least first and second metal regions separated by a dielectric region, an air gap formed at least partially within the dielectric region, a diffusion barrier positioned over the two metal regions covering a portion of the upper surface of the air gap, and an insulating layer positioned over the diffusion barrier sealing the upper surface of the air gap.