Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) pattering the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.

Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate. The gate structure includes an insulating cover. A second semiconductor layer is then conformally deposited. The deposited second semiconductor layer includes an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover. The amorphous portion is then removed using a selective etch. The remaining epitaxial portion forms faceted raised source-drain structures on either side of the transistor gate structure. A slope of the sloped surface for the facet is dependent on the process parameters used during the conformal deposition.

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOT substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Abstract: A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200° C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step.

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Abstract: A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200° C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step.

Abstract: A system for production of hydrogen comprises at least one steam reforming zone configured to receive a first fuel and steam to produce a first reformate gas stream comprising hydrogen using a steam reforming process. The system further comprises a mixed reforming zone configured to receive an oxidant to produce a second reformate gas stream comprising hydrogen, wherein the first reformate gas stream is sent to the mixed reforming zone to complete the reforming process.