Patents by Inventor David Barrera

David Barrera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5499204
    Abstract: A memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This storage strategy allows the memory cache to output a subset memory elements within a cache line quickly and in the original contiguous order. The invention may be advantageously incorporated in an instruction cache of superscalar data processor to provide a series of sequential instructions for execution.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: March 12, 1996
    Assignee: Motorola, Inc.
    Inventors: David Barrera, Dave Levitan, Bahador Rastegar, Paul C. Rossbach