Abstract: Nodulisporic acids (NAs) comprise a group of indole diterpenes known for their potent insecticidal activities; however, biosynthesis of NAs by its natural producer, Hypoxylon pulicicidum (Nodulisporium sp.) is exceptionally difficult to achieve. The identification of genes responsible for NA production could enable biosynthetic pathway optimization to provide access to NAs for commercial applications. Obtaining useful quantities of NAs using published fermentations methods is challenging, making gene knockout studies an undesirable method to confirm gene function. Alternatively, heterologous gene expression of H. pulicicidum genes in a more robust host species like Penicillium paxilli provides a way to rapidly identify the function of genes that play a role in NA biosynthesis. In this work, we identified the function of four secondary-metabolic genes necessary for the biosynthesis of nodulisporic acid F (NAF) and reconstituted these genes in the genome of P.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: Nodulisporic acids (NAs) comprise a group of indole diterpenes known for their potent insecticidal activities; however, biosynthesis of NAs by its natural producer, Hypoxylon pulicicidum (Nodulisporium sp.) is exceptionally difficult to achieve. The identification of genes responsible for NA production could enable biosynthetic pathway optimization to provide access to NAs for commercial applications. Obtaining useful quantities of NAs using published fermentations methods is challenging, making gene knockout studies an undesirable method to confirm gene function. Alternatively, heterologous gene expression of H. pulicicidum genes in a more robust host species like Penicillium paxilli provides a way to rapidly identify the function of genes that play a role in NA biosynthesis. In this work, we identified the function of four secondary-metabolic genes necessary for the biosynthesis of nodulisporic acid F (NAF) and reconstituted these genes in the genome of P.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: Nodulisporic acids (NAs) comprise a group of indole diterpenes known for their potent insecticidal activities; however, biosynthesis of NAs by its natural producer, Hypoxylon pulicicidum (Nodulisporium sp.) is exceptionally difficult to achieve. The identification of genes responsible for NA production could enable biosynthetic pathway optimization to provide access to NAs for commercial applications. Obtaining useful quantities of NAs using published fermentations methods is challenging, making gene knockout studies an undesirable method to confirm gene function. Alternatively, heterologous gene expression of H. pulicicidum genes in a more robust host species like Penicillium paxilli provides a way to rapidly identify the function of genes that play a role in NA biosynthesis. In this work, we identified the function of four secondary-metabolic genes necessary for the biosynthesis of nodulisporic acid F (NAF) and reconstituted these genes in the genome of P.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.

Abstract: An energy harvesting system includes a plurality of transducers. The transducers are configured to generate direct current (DC) voltages from a plurality of ambient energy sources. A sensor control circuit has a plurality of sensors configured to detect the DC signals from the plurality of transducers. A DC-to-DC converter is configured to supply an output voltage. A plurality of switches, each switch coupled between the DC-to-DC converter and a corresponding transducer of the plurality of transducers. The sensor control circuit enables one switch of the plurality of switches and disables the other switches of the plurality of switches based on a priority criterion.

Abstract: A system and method for simulating aging parameters of a System-on-Chip (SoC) integrated circuit is disclosed. A SoC integrated circuit is first divided into a plurality of blocks in accordance with the nature or the operating conditions of each block. The simulation of a digital circuit based block is performed by a static timing analyzer. The simulation of a mixed signal based block is performed by first employing a fresh device model to obtain relevant operation conditions, such as node voltages. Based upon the operation conditions and reliability characterization data, parameters degradation calculators assess aging characteristic factors of each block. In a subsequent simulation, a circuit simulator calculates the design corners of a SoC chip based upon the characteristic factors of each block.

Abstract: An energy harvesting system includes a plurality of transducers. The transducers are configured to generate direct current (DC) voltages from a plurality of ambient energy sources. A sensor control circuit has a plurality of sensors configured to detect the DC signals from the plurality of transducers. A DC-to-DC converter is configured to supply an output voltage. A plurality of switches, each switch coupled between the DC-to-DC converter and a corresponding transducer of the plurality of transducers. The sensor control circuit enables one switch of the plurality of switches and disables the other switches of the plurality of switches based on a priority criterion.

Abstract: A method includes selecting one of a plurality of existing transistor models for which fabrication and performance data are available, receiving first model data for a next-generation transistor based on target response data and the selected transistor model data, and simulating a response of a circuit including the next-generation transistor. The selection of the existing transistor model is based on target response data for the next-generation transistor for which fabrication and performance data are not available. The simulation is performed using the first transistor model data for the next-generation transistor. A difference between the target response and the simulated response of the next-generation transistor is calculated, and the first model data representing the next-generation transistor is stored in a computer readable storage medium if the performance data difference between the target response and the simulated response is below a threshold.

Abstract: An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract: An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.

Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.