Abstract: A network device includes a HomePNA modem and means for synchronizing its clock with clocks of other HomePNA modems in the network in order to communicate at a higher frequency band. In one embodiment, the synchronization is with pilot signals. In another, it is by correcting for clock differences. The upconversions may be via oversampling or via analog mixing. The downconversions may be via subsampling or via analog demixing.

Abstract: An operational amplifier includes an input stage for producing a a voltage signal in response to an input signal. An output stage includes an output transistor having a source coupled to a supply voltage and a gate coupled to receive the voltage signal. An output cascode transistor has a source coupled to a drain of the output transistor and a drain coupled to an output conductor. A gate control amplifier includes an input stage including a first input transistor having a control electrode coupled to the source of the output cascode transistor and an active load transistor, the input transistor and the active load transistor being coupled to a gate of the output cascode transistor. The gate control amplifier also includes a feedback amplifier having an input coupled to the source of the output cascode transistor and an output coupled to a control electrode of the active load transistor.

Abstract: In an on-line purchasing environment, a user is presented with a summary of each of a plurality of items. Upon selection of one of the items by the user, the user is presented with details of the selected item, as well as a list of possible recipients the item is to be sent to and a choice of shipping methods for delivering the item to chosen recipient(s). After receiving a selection of the chosen recipient(s) and shipping method(s) from the user, an order to purchase the item for the chosen recipient(s) via the shipping method(s) is quickly completed. Accordingly, a user may purchase an item for a plurality of recipients quickly and efficiently.

Abstract: A gamma reference voltage generator (10B) for an LCD display includes a control interface logic circuit (48) having an output bus coupled to inputs of a first register (46) having outputs coupled to inputs of a second register (42) the outputs of which are coupled to corresponding inputs of plurality of DACs (28). The control interface logic circuit receives gray scale codes representative of gamma reference voltages and transfers the codes via the output bus into the first register and controls further transfer of the codes to inputs of the DACs to instantaneously or rapidly update gamma correction voltages applied to the LCD display.

Abstract: A hybrid network includes telephone and non-telephone network media. The communication devices communicate along the hybrid network according to a media access plan. The non-telephone communication devices do not have collision detection although the telephone communication devices do. The non-telephone communication devices have higher power and sensitivity levels than the telephone communication devices. In some embodiments, the media access plan includes a registration timeslot for the non-telephone communication devices.

Abstract: A pole system comprises a shaft that includes tracks for mounting luminaires, street signs, bicycle racks, decorative signage, banners, traffic signals, pedestrian signals, or other items. In one embodiment, a pole system includes a shaft with two or more vertical tracks. Each track may have a dovetail shape and may be configured to receive mounting nuts for mounting items to the shaft. One or more vertical raceways separate from a center opening of the shaft may also be present.

Abstract: HPNA MxU network for an MxU, the MxU including a plurality of HPNA LANs, each of the HPNA LANs operating according to a synchronous communication specification. Each of the HPNA LANs includes a plurality of nodes, one of the nodes within each HPNA LAN being a gateway node, a selected one of the nodes within each HPNA LAN being defined a LAN-master node and each HPNA LAN is coupled with a WAN via the respective gateway node. The LAN-master nodes allow the gateway nodes to transmit within a selected HPNA LAN downstream signals during at least one time slot, and the LAN-master nodes allow the nodes other than the gateway nodes to transmit upstream signals within a selected HPNA LAN to the respective gateway or transmit HN signals within a selected HPNA LAN, between nodes other than the respective gateway nodes during at least another timeslot.

Abstract: HPNA MxU network for an MxU, the MxU including a plurality of HPNA LANs, each of the HPNA LANs operating according to a synchronous communication specification, each of the HPNA LANs including a plurality of nodes, one of the nodes within each HPNA LAN being a gateway node, a selected one of the nodes within each HPNA LAN being defined a LAN-master node, each HPNA LAN being coupled with a WAN via the respective gateway node, wherein communication lines within the HPNA LANs, directly coupled with the gateway nodes, are at least partially bound together, wherein the transmission direction within a selected HPNA LAN, by the respective gateway node, is defined downstream, wherein the transmission direction within a selected HPNA LAN, to the respective gateway node, is defined upstream, wherein the transmission direction within a selected HPNA LAN, between nodes other than the respective gateway nodes, is defined HN, wherein the LAN-master nodes allow the gateway nodes to transmit downstream signals during at leas

Abstract: A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor.

Abstract: Analog HPNA hub including at least one group of coils, the coils inducing HPNA signals there between, a plurality of filters, each of the filters coupled with a respective one of the coils and further coupled, via respective telephone wiring, with at least a respective HPNA node, wherein each of the filters enables transmission of HPNA data signals there through, and wherein each of the filters prevents transmission of conventional telephony signals there through.

Abstract: HPNA MxU network for an MxU, the MxU including a plurality of HPNA LANs, each of the HPNA LANs operating according to a synchronous communication specification, each of the HPNA LANs including a plurality of nodes, one of the nodes within each HPNA LAN being a gateway node, a selected one of the nodes within each HPNA LAN being defined a LAN-master node, each HPNA LAN being coupled with a WAN via the respective gateway node, wherein communication lines within the HPNA LANs, directly coupled to the gateway nodes, are at least partially bound together, wherein the transmission direction within a selected HPNA LAN, by the respective gateway node, is defined downstream, wherein the transmission direction within a selected HPNA LAN, to the respective gateway node, is defined upstream, wherein the transmission direction within a selected HPNA LAN, between nodes other than the respective gateway nodes, is defined HN, wherein the LAN-master nodes allow the gateway nodes to transmit downstream signals during at least

Abstract: A multi-stage differential amplifier with rail-to-rail input may utilize an output stage including first and second low-voltage rated transistors and first and second high-voltage transistors. The first low-voltage rated transistor and the first high-voltage rated transistor may be connected in series, and the second low-voltage rated transistor and the second high-voltage rated transistor may be connected in parallel. The low-voltage rated transistors are biased by signals provided by the input stage. In this way, the input stage controls the biasing of the low-voltage rated transistors in the output stage, thereby increasing the overall gain and speed of the amplifier system.

Abstract: A multi-stage differential amplifier with rail-to-rail input may utilize an output stage including first and second low-voltage rated transistors and first and second high-voltage transistors. The first low-voltage rated transistor and the first high-voltage rated transister may be connected in series, and the second low-voltage rated transistor and the second high-voltage rated transistor may be connected in parallel. The low-voltage rated transistors are biased by signals provided by the input stage. In this way, the input stage controls the biasing of the low-voltage rated transistors in the output stage, thereby increasing the overall gain and speed of the amplifier system.

Abstract: A high-speed transmitter, which generates an output signal stream having a specified spectral profile. The transmitter includes a Tomlinson-Harashima precoder, which is adapted to receive a sequence of input symbols having a given input constellation and to generate, responsive to the specified spectral profile, a corresponding sequence of precoded symbols. A transmit digital filter is adapted to apply a transmit filter response, in accordance with the specified spectral profile, to the precoded symbols so as to generate a corresponding sequence of output symbols, having a given output constellation, to be transmitted in the output stream.