Patents by Inventor David Benjamin Whalley

David Benjamin Whalley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for lookahead instruction fetching for processors utilizing tagless hit instruction caches
    Patent number: 8219756
    Abstract: Systems and methods may be provided for lookahead instruction fetching for processors. The systems and methods may include an L1 instruction cache, where the L1 instruction cache may include a plurality of lines of data, where each line of data may include one or more instructions. The systems and methods may also include a tagless hit instruction cache, where the tagless hit instruction cache may store a subset of the lines of data in the L1 instruction cache, where instructions in the lines of data stored in the tagless hit instruction cache may be stored with metadata indicative of whether a next instruction is guaranteed to reside in the tagless hit instruction cache, where an instruction fetcher may be arranged to have direct access to the L1 instruction cache and the tagless hit instruction cache, and where the tagless hit instruction cache may be arranged to have direct access to the L1 instruction cache.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: July 10, 2012
    Assignee: Florida State University Research Foundation
    Inventors: David Benjamin Whalley, Gary Scott Tyson, Stephen Roderick Hines
  • SYSTEMS AND METHODS FOR LOOKAHEAD INSTRUCTION FETCHING FOR PROCESSORS
    Publication number: 20090132766
    Abstract: Systems and methods may be provided for lookahead instruction fetching for processors. The systems and methods may include an L1 instruction cache, where the L1 instruction cache may include a plurality of lines of data, where each line of data may include one or more instructions. The systems and methods may also include a tagless hit instruction cache, where the tagless hit instruction cache may store a subset of the lines of data in the L1 instruction cache, where instructions in the lines of data stored in the tagless hit instruction cache may be stored with metadata indicative of whether a next instruction is guaranteed to reside in the tagless hit instruction cache, where an instruction fetcher may be arranged to have direct access to the L1 instruction cache and the tagless hit instruction cache, and where the tagless hit instruction cache may be arranged to have direct access to the L1 instruction cache.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 21, 2009
    Inventors: David Benjamin Whalley, Gary Scott Tyson, Stephen Roderick Hines