Patents by Inventor David BERMINGHAM

David BERMINGHAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thread issue control
    Patent number: 9753735
    Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbors within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 5, 2017
    Assignee: ARM Limited
    Inventors: Andreas Due Engh-Halstvedt, Ian Victor Devereux, David Bermingham, Jakob Axel Fries, Oskar Lars Flordal
  • THREAD ISSUE CONTROL
    Publication number: 20150227376
    Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbours within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.
    Type: Application
    Filed: January 14, 2015
    Publication date: August 13, 2015
    Inventors: Andreas Due ENGH-HALSTVEDT, Ian Victor DEVEREUX, David BERMINGHAM, Jakob Alex FRIES, Oskar Lars FLORDAL