Patents by Inventor David Bernard

David Bernard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128131
    Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Avishay Vaxman, Qintao Zhang, Jeffrey P. Koch, David P. Surdock, Wayne R. Swart, David J. Lee, Samphy Hong, Aldrin Bernard Vincent Eddy, Daniel G. Deyo
  • Publication number: 20240117682
    Abstract: A cutting element assembly includes a cutter support including a cutter bore. A cutting element is in the cutter bore and a resilient element is integral with the cutter support. The resilient element is longitudinally compressible and has a displacement of greater than 0.1 mm and optionally less than 2 mm. Another cutting assembly includes a cutter support coupled to multiple cutting elements. A resilient element of the cutter support is compressible based on a force applied to the cutter support through one or more of the cutting elements. The resilient element can include a slit in the cutter support. A slit may, for instance, extend perpendicular or transverse to an axis of the cutting elements and allow the cutter support to flex and close off or reduce a size of the slit when forces act on one or more of the cutting elements.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 11, 2024
    Inventors: David Robert Evan Snoswell, Ashley Bernard Johnson, Mauro Caresta, John Mervyn Cook
  • Publication number: 20240118992
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 11, 2024
    Applicant: Intel Corporation
    Inventors: Martin-Thomas Grymel, David Bernard, Martin Power, Niall Hanrahan, Kevin Brady
  • Patent number: 11940907
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 26, 2024
    Assignee: INTEL CORPORATION
    Inventors: Martin-Thomas Grymel, David Bernard, Niall Hanrahan, Martin Power, Kevin Brady, Gary Baugh, Cormac Brick
  • Patent number: 11921911
    Abstract: A peripheral device, for use with a host, comprises one or more compute elements a security module and at least one encryption unit. The security module is configured to form a trusted execution environment on the peripheral device for processing sensitive data using sensitive code. The sensitive data and sensitive code are provided by a trusted computing entity which is in communication with the host computing device. The at least one encryption unit is configured to encrypt and decrypt data transferred between the trusted execution environment and the trusted computing entity via the host computing device. The security module is configured to compute and send an attestation to the trusted computing entity to attest that the sensitive code is in the trusted execution environment.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: March 5, 2024
    Assignee: Microsoft Technology Licensing, LLC.
    Inventors: Stavros Volos, David Thomas Chisnall, Saurabh Mohan Kulkarni, Kapil Vaswani, Manuel Costa, Samuel Alexander Webster, Cédric Alain Marie Fournet, Richard Osborne, Daniel John Pelham Wilkinson, Graham Bernard Cunningham
  • Publication number: 20240072345
    Abstract: Provided is a battery assembly that includes an electrically-conductive housing (510A, 510B), one or more battery modules (512) electrically coupled to a busbar (522), the one or more battery modules and busbar being received in the housing. A non-woven core layer (506) is disposed between the busbar and electrically-conductive housing, the non-woven core layer comprising a plurality of fibers, the plurality of fibers comprising 60-100 wt % of oxidized polyacrylonitrile fibers. The non-woven core layer can exhibit a breakdown voltage of at least 0.9 kV at ambient conditions after exposure to 500° C. for 5 minutes.
    Type: Application
    Filed: December 23, 2021
    Publication date: February 29, 2024
    Inventors: Jose Maria Benito, Maria Jose Sanchez, Stephane Stephan, Pingfan Wu, Jean Louis Silvestre, David Bernard Andre Descoins
  • Patent number: 11909702
    Abstract: A data processing system is configured to perform a computer implemented method for facilitation of efficient processing of electronic messages via a network from message sources. The method includes receiving an electronic message including actionable object data and textual object data from a message source device. The actionable object data includes parameters actionable by at least one data processing transaction device to perform data processing transactions external to the network device and the textual object data including descriptors of the parameters actionable by the at least one data processing transaction device. The textual object data is operable by devices incompatible with the actionable object data. The method includes calculating an execution command for the data processing transaction in response to the actionable object data and based on at least the parameters of the actionable object data.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: February 20, 2024
    Assignee: Chicago Mercantile Exchange Inc.
    Inventors: Carrick John Pierce, Baris Mestanogullari, Ajay Kumar Jain, Agnes Casenave, David Bernard Barton, Nicholas Bandy
  • Patent number: 11893252
    Abstract: Processing can be performed to persistently record, in a log, a write I/O that writes first data to a target logical address. The processing can include: allocating storage for a first page buffer (PB) located at offsets in a PB pool of non-volatile storage of the log; enqueuing a request to an aggregation queue to persistently store the first data to the first PB of the log, wherein the request identifies the offsets of the PB pool of non-volatile storage which correspond to the first PB; and integrating the request into the aggregation queue. Integrating can include: determining whether a contiguous segment of the offsets of the request is adjacent to a second contiguous segment of the aggregation queue; and responsive to determining the contiguous segment is adjacent to the second contiguous segment, merging the first and second contiguous segments and generating an aggregated continuous segment.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: February 6, 2024
    Assignee: Dell Products L.P.
    Inventors: Svetlana Kronrod, Vladimir Shveidel, David Bernard, Vamsi K. Vankamamidi
  • Publication number: 20240036763
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.
    Type: Application
    Filed: September 12, 2023
    Publication date: February 1, 2024
    Applicant: Intel Corporation
    Inventors: Niall Hanrahan, Martin Power, Kevin Brady, Martin-Thomas Grymel, David Bernard, Gary Baugh, Cormac Brick
  • Publication number: 20240020031
    Abstract: Processing can be performed to persistently record, in a log, a write I/O that writes first data to a target logical address. The processing can include: allocating storage for a first page buffer (PB) located at offsets in a PB pool of non-volatile storage of the log; enqueuing a request to an aggregation queue to persistently store the first data to the first PB of the log, wherein the request identifies the offsets of the PB pool of non-volatile storage which correspond to the first PB; and integrating the request into the aggregation queue. Integrating can include: determining whether a contiguous segment of the offsets of the request is adjacent to a second contiguous segment of the aggregation queue; and responsive to determining the contiguous segment is adjacent to the second contiguous segment, merging the first and second contiguous segments and generating an aggregated continuous segment.
    Type: Application
    Filed: July 15, 2022
    Publication date: January 18, 2024
    Applicant: Dell Products L.P.
    Inventors: Svetlana Kronrod, Vladimir Shveidel, David Bernard, Vamsi K. Vankamamidi
  • Publication number: 20230399122
    Abstract: A method for determining at least one minimum power margin of a hybrid drive train for a transport vehicle, each drive element being associated with at least one power source and at least one power consumer. The method including a step of acquiring measurements of power parameters, a step of comparing each measurement with at least one limitation threshold, so as to deduce therefrom at least one gross margin, a step of converting the gross margins into refined margins expressed according to the same common magnitude, a step of transposing into standardised margins at least at one reference point, a step of determining a source power margin and a consumer power margin at said reference point and a step of determining the minimum power margin by selecting the lowest power margin.
    Type: Application
    Filed: November 8, 2021
    Publication date: December 14, 2023
    Inventors: David Bernard Martin Lemay, Jean-Philippe Jacques Marin
  • Publication number: 20230390242
    Abstract: Provided herein are compounds of Formula (I), or pharmaceutically acceptable salts thereof, pharmaceutical compositions that include a compound described herein (including pharmaceutically acceptable salts of a compound described herein) and methods of synthesizing the same. Also provided herein are methods of treating diseases and/or conditions with a compound of Formula (I), or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Sandrine Vendeville, David Bernard Smith, Leonid Beigelman, Vladimir Serebryany, Raymond F. Schinazi, Franck Amblard, Leda Bassit
  • Patent number: 11829279
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Martin-Thomas Grymel, David Bernard, Martin Power, Niall Hanrahan, Kevin Brady
  • Patent number: 11817887
    Abstract: Methods, apparatus, systems and articles of manufacture to compress data are disclosed. An example apparatus includes a data slicer to split a dataset into a plurality of blocks of data; a data processor to select a first compression technique for a first block of the plurality of blocks of data based on first characteristics of the first block; and select a second compression technique for a second block of the plurality of blocks of data based on second characteristics of the second block; a first compressor to compress the first block using the first compression technique to generate a first compressed block of data; a second compressor to compress the second block using the second compression technique to generate a second compressed block of data; and a header generator to generate a first header identifying the first compression technique and a second header identifying the second compression technique.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: November 14, 2023
    Assignee: Movidius Limited
    Inventors: Valentina Rigo, David Bernard, Peter McGlynn
  • Patent number: 11809248
    Abstract: A configurable connector is provided for a communication device, such as a gateway, that is located outdoors. The connector can engage with a corresponding interface of the gateway to provide communication signals and power signals to the communication device. The connector can be configured to select the power type provided to the communication device via the connector. The connector can have a first configuration to provide a first power type to the communication device or a second configuration to provide a second power type to the communication device. In the first configuration of the connector, power terminals of the connector can be connected directly to corresponding power wires providing the first power type. In the second configuration, the power terminals of the connector can be connected by jumpers to supplemental terminals in the connector that receive the second power type from the communication device.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: November 7, 2023
    Assignee: ADTRAN, INC.
    Inventors: Daniel M. Joffe, Jon Michael Chalmers, David Bernard Etzkorn
  • Patent number: 11789646
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: October 17, 2023
    Assignee: INTEL CORPORATION
    Inventors: Niall Hanrahan, Martin Power, Kevin Brady, Martin-Thomas Grymel, David Bernard, Gary Baugh, Cormac Brick
  • Patent number: 11771680
    Abstract: Provided herein are compounds of Formula (I), or pharmaceutically acceptable salts thereof, pharmaceutical compositions that include a compound described herein (including pharmaceutically acceptable salts of a compound described herein) and methods of synthesizing the same. Also provided herein are methods of treating diseases and/or conditions with a compound of Formula (I), or a pharmaceutically acceptable salt thereof.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: October 3, 2023
    Assignee: Aligos Therapeutics, Inc.
    Inventors: Sandrine Vendeville, David Bernard Smith, Leonid Beigelman, Vladimir Serebryany
  • Publication number: 20230289802
    Abstract: A general purpose blockchain (GPB) platform for creating, maintaining, and managing a distributed ledger. The GPB comprises multiple nodes, each configured to host a GPB for storing GPB arbitrary objects. Each GPB arbitrary object comprises an object data, wherein the object data being a structured or unstructured data; a basic data structure implemented in a data markup language that provides self-description of the object data with at least fields for storing the object's origin, the object's owner, the object's transfer history, object's modification/transformation history, the object type, and the object data; and a universal interface for providing an encapsulation or reference to the object data for accessing the object data and an transformation function to allow interoperability of object data of different formats. A plurality of GPB s collectively maintain consensus of changes of the stored GPB arbitrary objects with a plurality of other GPB s.
    Type: Application
    Filed: May 22, 2023
    Publication date: September 14, 2023
    Inventors: David Bernard THAW, Hyung Kyu KANG
  • Publication number: 20230244289
    Abstract: A configurable connector is provided for a communication device, such as a gateway, that is located outdoors. The connector can engage with a corresponding interface of the gateway to provide communication signals and power signals to the communication device. The connector can be configured to select the power type provided to the communication device via the connector. The connector can have a first configuration to provide a first power type to the communication device or a second configuration to provide a second power type to the communication device. In the first configuration of the connector, power terminals of the connector can be connected directly to corresponding power wires providing the first power type. In the second configuration, the power terminals of the connector can be connected by jumpers to supplemental terminals in the connector that receive the second power type from the communication device.
    Type: Application
    Filed: February 2, 2022
    Publication date: August 3, 2023
    Inventors: Daniel M. Joffe, Jon Michael Chalmers, David Bernard Etzkorn
  • Patent number: 11673070
    Abstract: Methods and systems for arranging audience members and musicians are described herein. An assembly of seats for an event location includes a plurality of musician seats and a plurality of audience seats. Each audience seat of the plurality of audience seats can be disposed in a particularly designated location on an event location surface relative to the plurality of musician seats such that each audience seat of the plurality of audience seats has an audience immersion score that is above a threshold minimal acceptable audience immersion score (MAAIS). The audience immersion score includes a musician adjacency component, a conductor position depth offset component, and a conductor position lateral offset component.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 13, 2023
    Assignee: INSIDEOUT CONCERTS, INC.
    Inventor: David Bernard