Patents by Inventor David Bernick

David Bernick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10131944
    Abstract: The invention also encompasses novel structures and methods comprising providing a molecular adapter for capture and manipulation of transfer RNA. The adaptor is bound to a tRNA molecule. The adaptor may be a cholesterol-linked DNA adapter oligonucleotide. The invention is useful in sequencing, identification, manipulation and modification of tRNA.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: November 20, 2018
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: David Bernick, Andrew Smith
  • Patent number: 10059984
    Abstract: Four novel sequences of type B DNA polymerases and variants and analogues thereof useful for applications involving DNA polymerization in high salt conditions.
    Type: Grant
    Filed: June 10, 2012
    Date of Patent: August 28, 2018
    Assignee: The Regents of the University of California
    Inventors: David Bernick, Andrew Holmes, Jeffrey Nivala
  • Publication number: 20170218439
    Abstract: The invention also encompasses novel structures and methods comprising providing a molecular adapter for capture and manipulation of transfer RNA. The adaptor is bound to a tRNA molecule. The adaptor may be a cholesterol-linked DNA adapter oligonucleotide. The invention is useful in sequencing, identification, manipulation and modification of tRNA.
    Type: Application
    Filed: March 24, 2015
    Publication date: August 3, 2017
    Applicant: The Regents of the University of California
    Inventors: David Bernick, Andrew Smith
  • Publication number: 20070064699
    Abstract: Techniques for routing data packets in a networked system. Specifically, a network system and methods of arbitrating data packets in a network system are provided. Switching devices are configured to receive one or more data packets, wherein each of the one or more data packets includes a respective source identification. The source identifications are compared to a source identification history mechanism, and the routing order of the data packets is determined based on the comparison.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Inventors: David Bernick, Robert Jardine, Marcelo de Azevedo
  • Publication number: 20070064597
    Abstract: Techniques for routing data packets in a networked system. Specifically, a network system and methods of arbitrating data packets in a network system are provided. Switching devices are configured to receive one or more data packets, wherein each of the one or more data packets is received at a respective input port each having a respective input port identification. The routing order of the data packets is determined based on the input port identification corresponding to the respective input port at which each of the data packets is received.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Inventors: David Bernick, Curtis Landry
  • Publication number: 20060020852
    Abstract: A method and system of servicing asynchronous interrupts in multiple processors executing a user program. Some of the exemplary embodiments may be a method comprising executing a user program on a first processor and a duplicate copy of the user program on a second processor, receiving an asynchronous interrupt by both the first and second processors, executing an interrupt service routine on the first processor at an agreed system call of the user program executed on the first processor, and executing an interrupt service routine on the second processor at the agreed system call of the user program executed on the second processor.
    Type: Application
    Filed: January 25, 2005
    Publication date: January 26, 2006
    Inventors: David Bernick, William Bruckert, David Garcia, Robert Jardine, James Klecka, Russell Rector
  • Publication number: 20060020850
    Abstract: In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.
    Type: Application
    Filed: July 20, 2004
    Publication date: January 26, 2006
    Inventors: Robert Jardine, David Bernick, Thomas Heynemann, James Smullen
  • Publication number: 20050246587
    Abstract: Method and system of determining whether a user program has made a system level call and thus whether the user program is uncooperative with fault tolerant operation. Some exemplary embodiments may be a processor-based method comprising providing information from a first processor to a second processor (the information indicating that a user program executed on the first processor has not made a system level call in a predetermined amount of time), and determining by the first processor, using information from the second processor, whether a duplicate copy of the user program substantially simultaneously executed in the second processor has made a system level call in the predetermined amount of time.
    Type: Application
    Filed: January 25, 2005
    Publication date: November 3, 2005
    Inventors: David Bernick, William Bruckert, David Garcia, Robert Jardine, Pankaj Mehra, James Smullen
  • Publication number: 20050223274
    Abstract: A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.
    Type: Application
    Filed: January 25, 2005
    Publication date: October 6, 2005
    Inventors: David Bernick, William Bruckert, David Garcia, Robert Jardine, James Klecka, Pankaj Mehra, James Smullen