Patents by Inventor David BLACK-SCHAFFER

David BLACK-SCHAFFER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150347298
    Abstract: Data can be stored in a multi-level cache hierarchy memory system by, for example, storing valid data associated with a cacheline in a primary location in a first cache memory location. The first cache memory also stores location information about an alternative location in a second cache memory associated with the cacheline. Space is allocated in the alternative location of the second cache memory to store data associated with the cacheline.
    Type: Application
    Filed: May 1, 2015
    Publication date: December 3, 2015
    Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER
  • Publication number: 20150347299
    Abstract: A placement policy enables the selective storage of cachelines in a multi-level cache hierarchy: Reuse behavior of a cacheline is tracked during execution of an application in both a first level cache memory and a second level cache memory. A cache placement policy for the cacheline is determined based on the tracked reuse behavior.
    Type: Application
    Filed: May 1, 2015
    Publication date: December 3, 2015
    Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER
  • Publication number: 20150143047
    Abstract: Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory. The system also includes a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer, and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer. Responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables which enables access to the cacheline without performing a tag comparison at the one of the first and second cache memories.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER, Stefanos KAXIRAS
  • Publication number: 20150143046
    Abstract: Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER, Stefanos KAXIRAS