Abstract: Compositions for the treatment of some orphan diseases and oral mucosal ulcers, many with similarities in terms of their anti-inflammatory and anti-oxidative activities, but also multiple differences in their observed abilities that can be combined to challenge the current, underlying pathophysiology. The orphan diseases of interest are Dupuytren's Contracture, Peyronie's Disease, Scleroderma, Raynaud's (or Renaud's) Phenomenon, chemotherapy/radiation induced oral mucosal ulceration, and aphthous ulcers; and more frequent skin issues of skin damage from cuts, abrasions, and burns; aging skin changes, and toe nail fungus. These can be treated with the disclosed compositions with the proper combination and alteration of ingredients inclusive of alpha-pinene, an aloe vera preparation, and a shea butter preparation. A process for preparation of such ingredients in a water-in-oil emulsion is described herein.

Abstract: The present disclosure provides a method and a system for migrating a virtual file server. In an example of a method, a virtual file server is migrated from a first storage to a second storage, wherein the virtual file server comprises a server layer and a data layer. Identity information is retrieved from the server layer from the server layer for the second storage. The identity information is updated so instantiation of the virtual file server on the second storage appears the same as on the first storage.

Abstract: Compositions for the treatment of some orphan diseases and oral mucosal ulcers, many with similarities in terms of their anti-inflammatory and anti-oxidative activities, but also multiple differences in their observed abilities that can be combined to challenge the current, underlying pathophysiology. The orphan diseases of interest are Dupuytren's Contracture, Peyronie's Disease, Scleroderma, Raynaud's (or Renaud's) Phenomenon, chemotherapy/radiation induced oral mucosal ulceration, and aphthous ulcers; and more frequent skin issues of skin damage from cuts, abrasions, and burns; aging skin changes, and toe nail fungus. These can be treated with the disclosed compositions with the proper combination and alteration of ingredients inclusive of alpha-pinene, an aloe vera preparation, and a shea butter preparation. A process for preparation of such ingredients in a water-in-oil emulsion is described herein.

Abstract: The present disclosure provides a method and a system for migrating a virtual file server. In an example of a method, a virtual file server is migrated from a first storage to a second storage, wherein the virtual file server comprises a server layer and a data layer. Identity information is retrieved from the server layer from the server layer for the second storage. The identity information is updated so instantiation of the virtual file server on the second storage appears the same as on the first storage.

Abstract: The present disclosure provides a method and a system for migrating a virtual file server. In an example of a method, a virtual file server is migrated from a first storage to a second storage, wherein the virtual file server comprises a server layer and a data layer. Identity information is retrieved from the server layer from the server layer for the second storage. The identity information is updated so instantiation of the virtual file server on the second storage appears the same as on the first storage.

Abstract: A storage system to process storage that includes a storage management module and a plurality of redundant array of independent disks (RAID) storage groups that includes storage drives to have a plurality of redundancy levels. The storage management module is configured to detect a failure of a storage drive of a first storage RAID storage group of the plurality of RAID groups which results in the first RAID storage group having at least two fewer redundant storage drives as compared to a second RAID storage group, and in response to detection of the failure of the first RAID storage group, select a storage drive from a second RAID storage group of the plurality of RAID storage groups, which has a plurality of redundancy levels, as a donor spare storage drive for the failed storage drive of the first RAID storage group.

Abstract: A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

Abstract: A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

Abstract: A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

Abstract: A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

Abstract: A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate, The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory ("DRAM") device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ("ZBT"), or pipeline burst static random access memory ("SRAM") devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a "Wait" pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater.