Abstract: A memory subsystem includes a plurality of storage elements and a controller coupled to a switch. In a first mode, the controller controls information transfer to and from the plurality of storage elements. Also coupled to the switch is a debug port controller. The debug port controller can be activated to set the switch to a second mode which permits the debug port controller to control information transfer to and from the plurality of storage element. More specifically, read data can be transferred from the plurality of storage elements to another device, via the switch and a buffer in the debug port controller. Similarly, write data can be transferred to the plurality of storage elements from another device via the buffer in the debug port controller and the switch. The debug port controller may be activated, deactivated, and controlled by setting values in one or more configuration registers.

Abstract: A memory subsystem includes a plurality of storage elements and a controller coupled to a switch. In a first mode, the controller controls information transfer to and from the plurality of storage elements. Also coupled to the switch is a debug port controller. The debug port controller can be activated to set the switch to a second mode which permits the debug port controller to control information transfer to and from the plurality of storage element. More specifically, read data can be transferred from the plurality of storage elements to another device, via the switch and a buffer in the debug port controller. Similarly, write data can be transferred to the plurality of storage elements from another device via the buffer in the debug port controller and the switch. The debug port controller may be activated, deactivated, and controlled by setting values in one or more configuration registers.