Patents by Inventor David Braddock
David Braddock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11668552Abstract: A square gauge apparatus configured for being selectively and removably mounted on a leg of a carpenter's square has a ledge having a ledge first surface and an opposite ledge second surface, the ledge first and second surfaces being parallel and offset, a first abutment extending from the ledge and having a first abutment front surface that is perpendicular to the ledge first surface, a second abutment extending from the ledge opposite the first abutment and having a second abutment front surface that is perpendicular to the ledge second surface and parallel to and coplanar with the first abutment front surface, and a slot formed adjacent to the ledge between the first and second abutments, the slot having a slot end surface that is parallel to and coplanar with the first and second abutment front surfaces.Type: GrantFiled: October 19, 2020Date of Patent: June 6, 2023Inventor: Lawrence David Braddock
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Publication number: 20200158485Abstract: A multi-function pair of square gauges for a steel square, the more common of which are referred to as framing or rafter squares. The square gauges give the steel square 90 degree abutments which are in precise vertical alignment with the square blades vertical edge, which essentially turn a carpenter's square into a try square. They also give the square ledges which self-support the square when in normal use. They can also be positioned on the square as a length or depth gauge for marking framing stud layout or repetitive cut lines, and can also be positioned as an improved set of stair or rafter gauges.Type: ApplicationFiled: November 20, 2018Publication date: May 21, 2020Inventor: Lawrence David Braddock
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Publication number: 20080282983Abstract: A filament, heat shield, supporting base comprised of SiC with ceramic insulators and top plate that together form an effusion assembly for use in the vacuum evaporation, molecular beam epitaxy, and ultra high vacuum deposition of epitaxial materials. The effusion assembly used together with a crucible and source material allow for the vacuum evaporation of species above 1250° C. when quantities of reactive gaseous species such as oxygen, sulphur, or reactive nitrogen are present in the deposition chamber. The relative chemical inertness of SiC even at elevated temperatures allows the SiC filament assembly to be used at high temperature especially in the presence of oxygen for the high purity epitaxial nucleation and growth layered electronic materials including semiconductors, metals, oxides, dielectric multilayer stacks, sulfides and oxides.Type: ApplicationFiled: December 8, 2004Publication date: November 20, 2008Inventor: Walter David Braddock, IV
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Publication number: 20080157073Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor sure from the second insulating oxide layer. A refractory mal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventor: Walter David Braddock
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Patent number: 7190037Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.Type: GrantFiled: February 9, 2005Date of Patent: March 13, 2007Assignee: Osemi, Inc.Inventor: Walter David Braddock, IV
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Patent number: 7187045Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer.Type: GrantFiled: July 16, 2002Date of Patent: March 6, 2007Assignee: OSEMI, Inc.Inventor: Walter David Braddock
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Patent number: 6989556Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.Type: GrantFiled: June 6, 2002Date of Patent: January 24, 2006Assignee: Osemi, Inc.Inventor: Walter David Braddock
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Patent number: 6936900Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.Type: GrantFiled: August 10, 2000Date of Patent: August 30, 2005Assignee: Osemi, Inc.Inventor: Walter David Braddock, IV
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Publication number: 20050075950Abstract: A method for managing supply chain relationships between a plurality of participants in the supply chain is described. The method includes receiving electronic messages exchanged between the supply chain participants and parsing the received messages for one or more of participant identifier information and contextual data relating to a business event. The method also includes analyzing a performance criteria for the supply chain based on data parsed from the electronic messages and providing data relating to supply chain management to the relevant participants based on the analysis.Type: ApplicationFiled: July 16, 2003Publication date: April 7, 2005Inventors: Daniel Lewis, David Braddock, John Cooney
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Publication number: 20040207029Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first conductive oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.Type: ApplicationFiled: July 16, 2002Publication date: October 21, 2004Inventor: Walter David Braddock
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Publication number: 20040206979Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.Type: ApplicationFiled: June 6, 2002Publication date: October 21, 2004Inventor: Walter David Braddock
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Patent number: 6670651Abstract: A self-aligned enhancement mode metal-sulfide-oxide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide-oxide gate insulating structure. The gallium sulfide-oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer.Type: GrantFiled: August 12, 2000Date of Patent: December 30, 2003Assignee: Osemi, Inc.Inventor: Walter David Braddock
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Patent number: 6573528Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.Type: GrantFiled: October 12, 2001Date of Patent: June 3, 2003Inventor: Walter David Braddock
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Patent number: 6451711Abstract: A system for coating the surface of compound semiconductor wafers includes providing a single-wafer epitaxial production system in a cluster-tool architecture with a loading, storage, and transfer modules, a III-V deposition chamber, and an insulator deposition chamber. The compound semiconductor wafer is placed in the loading and transfer module and the pressure is reduced to less than 5×10−10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The single wafer is then moved through the transfer module to the insulator chamber and an insulating cap layer is formed by thermally evaporating molecules, consisting essentially of gallium and oxygen, from an effusion cell using a thermal evaporation source that utilizes a metallic iridium crucible that is manufactured using the electroforming process.Type: GrantFiled: August 4, 2000Date of Patent: September 17, 2002Assignee: Osemi, IncorporatedInventor: Walter David Braddock, IV
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Patent number: 6445015Abstract: A self-aligned enhancement mode metal-sulfide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide gate insulating structure. The gallium sulfide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer.Type: GrantFiled: August 11, 2000Date of Patent: September 3, 2002Assignee: Osemi, IncorporatedInventor: Walter David Braddock
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Publication number: 20020113285Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.Type: ApplicationFiled: October 12, 2001Publication date: August 22, 2002Inventor: Walter David Braddock
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Patent number: 5800692Abstract: A preseparation processor for use in capillary electrophoresis is described. The preseparation processor contains sample processing material, preferably in the form of a membrane, for use in concentrating or chemically processing a sample, or catalyzing a chemical reaction. It is particularly suited to the concentration of dilute samples or the purification of contaminated samples. The preseparation processor facilitates reliable and reproducible separation of analytes by eliminating inconsistencies caused by a reversal of the electroosmotic flow otherwise induced by the sample processing material.Type: GrantFiled: April 17, 1995Date of Patent: September 1, 1998Assignee: Mayo Foundation for Medical Education and ResearchInventors: Stephen Naylor, Andrew J. Tomlinson, Linda M. Benson, Walter David Braddock, Robert P. Oda