Abstract: A flow meter system includes a first ultrasonic transducer array to be flush-mounted to a pipe. The system also includes a second ultrasonic transducer array to be flush-mounted to the pipe. The system further includes a controller coupled to the first and second ultrasonic transducer arrays and configured to cause bidirectional beam steering between the first and second ultrasonic transducer arrays.

Abstract: The present disclosure provides a power switch for use in a power management system including a power source for supplying an electrical current, and a load for receiving the electric current upon establishing a circuit with the power source. The power switch includes a motion sensor, a timer, and a gate. The motion sensor is configured to sense a motion related to an operation of the load and generate an idle signal when the sensed motion is below a predetermined threshold. The timer is coupled with the motion sensor, and it is configured to activate a power-off signal upon detecting the idle signal for a predetermined time period. The gate is coupled with the timer, and it is configured to either complete the circuit when the power-off signal is inactive or break up the circuit when the power-off signal is active.

Abstract: A flow meter system includes a first ultrasonic transducer array to be flush-mounted to a pipe. The system also includes a second ultrasonic transducer array to be flush-mounted to the pipe. The system further includes a controller coupled to the first and second ultrasonic transducer arrays and configured to cause bidirectional beam steering between the first and second ultrasonic transducer arrays.

Abstract: A micromachined ultrasonic transducer (MUT) circuit, which has a MUT with a MUT membrane that can vibrate back and forth to transmit an ultrasonic wave, electrically controls the movement of the MUT membrane by controllably transferring energy to the MUT membrane, thereby allowing the MUT membrane to transmit substantially any desired ultrasonic wave.

Abstract: A micromachined ultrasonic transducer (MUT) circuit, which has a MUT with a MUT membrane that can vibrate back and forth to transmit an ultrasonic wave, electrically controls the movement of the MUT membrane by controllably transferring energy to the MUT membrane, thereby allowing the MUT membrane to transmit substantially any desired ultrasonic wave.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.