Patents by Inventor David Brian Glasco

David Brian Glasco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10042804
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: August 7, 2018
    Assignee: Sanmina Corporation
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Publication number: 20150074325
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Application
    Filed: November 3, 2014
    Publication date: March 12, 2015
    Applicant: MEMORY INTEGRITY, LLC
    Inventors: Charles Edward Watson, JR., Rajesh Kota, David Brian Glasco
  • Patent number: 8898254
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 25, 2014
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Publication number: 20140013079
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: Memory Integrity, LLC
    Inventors: Charles Edward Watson, JR., Rajesh Kota, David Brian Glasco
  • Patent number: 8572206
    Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: October 29, 2013
    Assignee: Memory Integrity, LLC
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Patent number: 8185602
    Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: May 22, 2012
    Assignee: Newisys, Inc.
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Publication number: 20120089787
    Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Inventors: Charles Edward Watson, JR., Rajesh Kota, David Brian Glasco
  • Patent number: 7577755
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: August 18, 2009
    Assignee: Newisys, Inc.
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
  • Patent number: 7418517
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: August 26, 2008
    Assignee: Newisys, Inc.
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
  • Patent number: 7346744
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for improving the accuracy of information available to a cache coherence controller are provided in order to allow the cache coherence controller to reduce the number of transactions in a multiple cluster system. Non-change probes and augmented non-change probe responses are provided to acquire state information in remote clusters without affecting the state of the probed memory line. Augmented probe responses associated with shared and invalidating probes are provided to update state information in a coherence directory during read and read/write probe requests.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 18, 2008
    Assignee: Newisys, Inc.
    Inventor: David Brian Glasco
  • Patent number: 7334089
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. State information is provided to the remote data cache using various mechanisms including a coherence directory and augmented source done messages.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: February 19, 2008
    Assignee: Newisys, Inc.
    Inventor: David Brian Glasco
  • Patent number: 7281055
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: October 9, 2007
    Assignee: Newisys, Inc.
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Patent number: 7251698
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: July 31, 2007
    Assignee: Newisys, Inc.
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Patent number: 7222262
    Abstract: Techniques and devices are provided for injecting transactions within computer systems having a plurality of multi-processor clusters. Each cluster includes a plurality of nodes, including processors, a service processor and an interconnection controller interconnected by point-to-point intra-cluster links. The processors and the interconnection controller in each cluster make transactions via an intra-cluster transaction protocol. Inter-cluster links are formed between interconnection controllers of different clusters. Each of the processors and the interconnection controller in a cluster has a test interface for communicating with the service processor. The service processor is configured to make an injected transaction according to the intra-cluster transaction protocol via one of the test interfaces.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: May 22, 2007
    Assignee: Newisys, Inc.
    Inventors: Guru Prasadh, David Brian Glasco, Rajesh Kota, Scott Diesing
  • Patent number: 7155525
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: December 26, 2006
    Assignee: Newisys, Inc.
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Patent number: 7039740
    Abstract: An interconnection controller for use in a computer system having a plurality of processor clusters is described. Each cluster includes a plurality of local nodes and an instance of the interconnection controller. The interconnection controller is operable to transmit locally generated interrupts to others of the clusters, and remotely generated interrupts to the local nodes. The interconnection controller is further operable to aggregate locally generated interrupt responses for transmission to a first remote cluster from which a first interrupt corresponding to the locally generated responses was generated. The interconnection controller is also operable to aggregate remotely generated responses for transmission to a first local node from which a second interrupt corresponding to the remotely generated responses was generated. A computer system employing such an interconnection controller is also described.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: May 2, 2006
    Assignee: Newisys, Inc.
    Inventors: David Brian Glasco, Carl Zeitler
  • Patent number: 6920532
    Abstract: Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. The cache coherence controller is operable to initiate eviction of an entry in its directory corresponding to a modified copy of a memory line by sending a request to merge an empty data field with the modified copy of the memory line to a corresponding memory controller.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: July 19, 2005
    Assignee: Newisys, Inc.
    Inventors: David Brian Glasco, Rajesh Kota, Sridhar K. Valluru
  • Publication number: 20040236912
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. State information is provided to the remote data cache using various mechanisms including a coherence directory and augmented source done messages.
    Type: Application
    Filed: May 20, 2003
    Publication date: November 25, 2004
    Applicant: Newisys, Inc. A Delaware corporation
    Inventor: David Brian Glasco
  • Publication number: 20040153507
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Applicant: Newisys, Inc. A Delaware corporation
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
  • Publication number: 20040098475
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.
    Type: Application
    Filed: November 19, 2002
    Publication date: May 20, 2004
    Applicant: Newisys, Inc., A Delaware Corporation
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota