Patents by Inventor David Brian Oraboni, JR.

David Brian Oraboni, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power semiconductor package having integrated inductor, resistor and capacitor
    Patent number: 11309233
    Abstract: A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: April 19, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, Jr., Long-Ching Wang, Jian Yin
  • POWER SEMICONDUCTOR PACKAGE HAVING INTEGRATED INDUCTOR, RESISTOR AND CAPACITOR
    Publication number: 20210082793
    Abstract: A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.
    Type: Application
    Filed: February 25, 2020
    Publication date: March 18, 2021
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, JR., Long-Ching Wang, Jian Yin
  • POWER SEMICONDUCTOR PACKAGE HAVING INTEGRATED INDUCTOR AND METHOD OF MAKING THE SAME
    Publication number: 20210082790
    Abstract: A power semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a first metal clip, a second metal clip, an inductor assembly, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. A method for fabricating a power semiconductor package. The method comprises the steps of providing a lead frame; attaching a low side FET and a high side FET to the lead frame; mounting a first metal clip and a second metal clip; mounting an inductor; forming a molding encapsulation; and applying a singulation process.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, JR., Long-Ching Wang