Abstract: A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in a second region.

Abstract: A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.

Abstract: A process of forming a multi-layer electronic composite structure. The process includes providing at least one core including at least one plane of at least one electrically conducting material with a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material. The at least one core includes a plurality of placed through holes formed therethrough. At least one pad is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device and also prevents solder from entering the at least one plated through hole.

Abstract: The present invention provides a new device and technique for enhancing the electrical properties of the thick metal backer/adhesive bond/ground plane interface. The enhanced electrical properties are obtained by micro-roughening a connection surface of the thick metal backer prior to forming the thick metal backer/adhesive bond/ground plane interface.

Abstract: Disclosed is a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a novel fixture for holding the substrate and a novel mask for 1-step photolithographic exposure. The result of the invention is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.

Abstract: A process of forming a multi-layer electronic composite structure. The process includes providing at least one core including at least one plane of at least one electrically conducting material with a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material. The at least one core includes a plurality of plated through holes formed therethrough. At least one pad is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device and also prevents solder from entering the at least one plated through hole.

Abstract: The present invention provides a new device and technique for enhancing the electrical properties of the thick metal backer/adhesive bond/ground plane interface. The enhanced electrical properties are obtained by micro-roughening a connection surface of the thick metal backer prior to forming the thick metal backer/adhesive bond/ground plane interface.

Abstract: A liquid crystal display is provided wherein a plurality of liquid crystal display tiles are arranged in a matrix and are electrically interconnected to a tile carrier by depositing an electrically conductive metal on a sidewall edge of the liquid crystal display such as by plating, evaporation, or sputtering. Also provided is the method for forming the liquid crystal display.

Abstract: A technique is disclosed for forming a chip cube from a plurality of chips laminated together in front-to-back relationship, the edges of the chip forming a cube face having a set of connectors for each chip thereon. A number "X" of functional chips is required for the operation, and "X+Y" is the number of chips provided in the stack such that there is Y number of chips greater than the number of functional chips required. If any number of chips equal to Y or less are found to be defective, there are enough chips remaining to perform the required function. Thereafter X number of good chips are connected to output circuitry through an interposer. Electrical connectors are provided on all of the IC chips. Contact pads for all of the connectors are provided on one face, and outlet pads are provided on the opposite face of the interposer for at least Y number of outlets. The interposer has vias at least equal to the number of outlet pads.

Abstract: A plurality of liquid crystal display tiles arranged in a matrix are electrically interconnected to a tile carrier by wire bonds.

Abstract: A process of forming a multi-layer electronic composite structure. At least one core including at least one functional plane of at least one electrically conducting material having a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material is provided. The at least one core includes a plurality of plated through holes formed therethrough. A pad of an electrically-conducting material is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device. The pad also prevents solder from entering the at least one plated through hole. Additionally, the pad provides an electrical connection between the electronic device and the at least one core.

Abstract: An interposer including a first face and a second face opposite the first face and at least one electrically conductive plane. The at least one electrically conductive plane functions as a power, ground, or signal plane. At least one electrically insulating plane is positioned on opposite sides of the at least one electrically conductive plane. A plurality of plated through holes are formed through the at least one electrically conductive planes and the at least two electrically insulating planes. The through holes are selectively electrically joined to the at least one electrically conductive plane. At least one passive electronic structure is positioned within the interposer structure.

Abstract: A technique of connecting a first member having a first face to a second member having a second face utilizing dendrites is provided. Dendrites are formed on one face of the first member in a given configuration. Dendrite receiving and securing material, preferably solder, is formed on a face of the second member in a configuration confirming substantially to the given configuration of the dendrites on the one face. The first and second members are then placed in a position relative to each other with the dendrites on the one face of the first member in contact with the dendrite receiving and engaging material on the face of the second member. An airtight seal is then provided between the first and second faces surrounding the dendrites and dendrite receiving and engaging material, which forms a sealed chamber between the first and second members.

Abstract: A cap for attaching a chip or other device to a multi-layer electronic structure. The cap includes a plurality of pads of an electrically-conducting material attached over plated through holes of the multi-layer electronic structure. Each of the pads includes a flat upper surface for attaching the chip or other device to the multi-layer structure, provides an electrical connection between the chip or other device and the multi-layer structure, and seals the through holes to prevent solder from entering the plated through hole. The pads are physically isolated from each other.

Abstract: A support structure is attached to the front or back side of a flexible circuit by direct mounting to the flexible circuit flat ribbon cable, thereby providing a stress-free region of the cable in which the flexible circuit electrical components can be mounted. The support structure comprises a flat ring that is attached to the cable by adhesive, soldering, or mechanical fastening. The flat ring mounts on one side of the flat ribbon cable and encloses an area of the cable that is sufficiently large for the mounting of the flexible circuit electrical components. The flat ribbon cable within the enclosed area is held flat and free from stress, even as the cable is handled. Thus, any components mounted within the enclosed area are not subjected to bending moments. The invention also can be incorporated into cable connectors, such as multi-pin connectors at the ends of cables, and can include support hooks and air cooling baffles.

Abstract: A method for making a printed circuit board with a flush surface land begins by forming a multi-layer printed circuit board with a recess in a surface dielectric layer. Then, a hole is drilled into or through the printed circuit board; the hole communicates with the recess. After the recess is formed, a conductive material is provided in the recess to form a surface land and provided on an inner surface of the hole to form a plated hole which is electrically connected to the surface land. The conductive material in the recess has a thickness substantially equal to a depth of the recess such that the surface land is flush with an adjacent surface of the dielectric surface layer.