Abstract: A memory circuit for storing parsimonious data and intended to receive an input vector of size Iz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number Iz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.

Abstract: A memory circuit for storing parsimonious data and intended to receive an input vector of size lz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number lz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.

Abstract: A shift-and-add multiplier able to perform multiplication operations by multiplicative values, configured to receive as input a binary value and to deliver the product of the value and of a respective multiplicative value. It includes a set of shift units, each connected to the input and configured to perform a bit shift of the value received at the input, varying from one shift unit to another; and a set of summation units, configured to sum the outputs of the shift units. It includes a set of multiplexing unit(s) connected between the set of shift units and the set of summation unit(s), and a control unit configured to control the set of multiplexing unit(s) to select respective outputs of the shift units according to the multiplicative value and to deliver them to the set of summation unit(s).

Abstract: This electronic calculator comprises a plurality of electronic calculation blocks, each of which is configured to implement one or more respective processing layers of an artificial neural network. The calculation blocks are of at least two different types among: a first type with fixed topology, fixed operation, and fixed parameters, a second type with fixed topology, fixed operation, and modifiable parameters, and a third type with modifiable topology, modifiable operation, and modifiable parameters. For each processing layer implemented by the respective calculation block, the topology is a connection topology for each artificial neuron; the operation is a type of processing to be performed for each artificial neuron; and the parameters include values able to be determined via training of the neural network.