Abstract: Disclosed is a voltage regulator having input terminals for connection to a voltage supply, output terminals for supplying power to a circuit at a predetermined maximum supply voltage, and a voltage regulator circuit connecting the input and output terminals. The voltage regulator circuit has a first supply path connecting first input and output terminals, a second supply path connecting the other input and output terminals, and an active component arranged between the first input and output terminals. A feedback control loop connected to a control terminal of the active component is arranged to sense the voltage on the output side of the active component and, when the voltage is above the maximum supply voltage, limit the output voltage to the maximum supply voltage, and, when the voltage is below the maximum supply voltage, signal the active component to pass power from the input terminals to the output terminals.

Abstract: To receive a spread spectrum signal without access to the timing information of the transmitter, it is necessary to synchronise timing at the receiver. Assuming each symbol is represented by n chips, synchronisation is done using a search algorithm that receives n?1 chips and determines whether k1 of those chips match, repeating the procedure until they do. Since only n?1 chips are sampled, the method cycles through possible timings until the correct timing is found. After synchronisation, a variety of techniques are used to maintain synchronisation until the complete message has been retrieved, many of which techniques abort message receipt if fewer than various predetermined numbers of chips match possible symbols. The predetermined numbers k, k3, k4, k5 may vary for different parts of the message.

Abstract: A circuit for controlling a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes frequency dividers with selectable divisors for the reference and feedback signals, and a phase detector having a charge pump output circuit with selectable output current ranges. During acquisition of phase lock by the PLL, the divisors for the reference and feedback signal frequency dividers are increased by the same factor, and the charge pump current range is increased by the same ratio. As a result, the reference rate is decreased as the charge pump current range is increased simultaneously by the same ratio. Meanwhile, the linear loop bandwidth and phase margin remain substantially constant.