Abstract: Techniques are disclosed for estimating the signal propagation delays within a circuit, based on a description of the circuit written in a hardware description language (HDL), such as a register transfer language (RTL). Assignment statements in the description which describe the performance of a logical function are modeled using logic gates which perform the function described. A particular function may be modeled using one or more logic gates depending on the number of inputs to the function. The delay associated with performance of the function is estimated by estimating the delay through the circuit used to model the function. Estimates for multiple functions may be combined to estimate the total delay associated with a particular signal path through a circuit.

Abstract: Systems, methodologies, media, and other embodiments associated charge rationing aware scheduling are provided. One exemplary system includes a scheduling logic configured to determine the charge rationing status of a processor, to examine properties of executables waiting to be executed on the processor, and to select an executable for execution by the processor based on the charge rationing status of the processor and the properties of the executable.

Abstract: Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations associated with dynamic and static power related parameters of a circuit design. The power characterizations can be determined prior to circuit design optimizations, stored and utilized during circuit design optimizations.

Abstract: The convergence speed of a computer-implemented genetic optimization process is improved through the correction of child chromosomes containing undesirable gene combinations. Undesirable gene combinations may be identified through application of heuristic techniques, statistical techniques, or a combination of the two.