Abstract: Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.

Abstract: Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.

Abstract: A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Abstract: A method of sending a command from a slave storage device to a master host includes receiving an initial command from the master host. A callback response containing a requested command triggered by the initial command is sent by the slave storage device. In one embodiment, the master host is a Universal Flash Storage (UFS) host and the slave storage device is a UFS storage device. In one embodiment, the initial command is a start stop unit (SSU) command with a power condition field of sleep or powerdown and the requested command is a read buffer command. In another embodiment, the initial command is a start stop unit (SSU) command with a power condition field of active and the requested command is a write buffer command.

Abstract: A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Abstract: A system and method for time stamp synchronization are disclosed. In one embodiment, first and second devices are provided. The second device receives a first time stamp of the first device, wherein the first time stamp was generated in response to a time stamp synchronization event common to the first and second devices; generates a second time stamp of the second device in response to the time stamp synchronization event, wherein the first and second time stamps are in different time domains; and correlates the first and second time stamps, wherein correlating the first and second time stamps provide a relationship between the time domains because the first and second time stamps were both generated with respect to the same time stamp synchronization event common to the first and second devices.

Abstract: A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Abstract: A method of sending a command from a slave storage device to a master host includes receiving an initial command from the master host. A callback response containing a requested command triggered by the initial command is sent by the slave storage device. In one embodiment, the master host is a Universal Flash Storage (UFS) host and the slave storage device is a UFS storage device. In one embodiment, the initial command is a start stop unit (SSU) command with a power condition field of sleep or powerdown and the requested command is a read buffer command. In another embodiment, the initial command is a start stop unit (SSU) command with a power condition field of active and the requested command is a write buffer command.

Abstract: A system and method for time stamp synchronization are disclosed. In one embodiment, first and second devices are provided. The second device receives a first time stamp of the first device, wherein the first time stamp was generated in response to a time stamp synchronization event common to the first and second devices; generates a second time stamp of the second device in response to the time stamp synchronization event, wherein the first and second time stamps are in different time domains; and correlates the first and second time stamps, wherein correlating the first and second time stamps provide a relationship between the time domains because the first and second time stamps were both generated with respect to the same time stamp synchronization event common to the first and second devices.

Abstract: The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

Abstract: The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

Abstract: The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

Abstract: The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as a repeater in a communication system. The PHY repeater supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. When the pass all symbols, pass violation symbols and pass line states modes are enabled, the PHY device operates as a "transparent" repeater. The repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The repeater also allows line states to be repeated without station management software. A single repeater may be used to couple two stations or multiple repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Abstract: Embodiments of the present invention provide methods and circuits for testing the hybrid capabilities of a station before the station is connected into an FDDI-II hybrid ring. One embodiment tests hybrid mode operation of an FDDI-II non-monitor station by creating a loopback ring, generating cycles for isochronous transmission on the loopback ring, and measuring the progress of the cycles around the loopback ring. The loopback ring created may be internal to a single integrated circuit, internal to a single slave station, or limited to a pair of stations, such as a concentrator and a single attachment station. Another embodiment provides a circuit for use in station on an FDDI-II ring. The circuit includes a loopback circuit which may be configured to create a hybrid ring and a cycle generator for generating cycles on the hybrid ring.

Abstract: In a communication network, an efficient link error monitor is provided that completely relieves the microprocessor of computing the link error rate and comparing it with link error rate thresholds. The link error rate computation and the comparison are performed by the physical layer of a communication station. The physical layer generates an interrupt to the microprocessor only if a threshold is crossed and a microprocessor action may be required. The physical layer includes a number of registers that can be conveniently written by the microprocessor to designate the thresholds and monitor the link errors. The link error rate is estimated using a simple estimator that provides a realistic link error rate estimate even at early stages of operation when few link errors have been detected and when, therefore, little statistical information on the link error rate exists.