Abstract: An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a circuit core (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

Abstract: An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Abstract: An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

Abstract: An electronic device can include a substrate (12) having a primary surface (14), a second surface (16, 22) opposite the primary surface (14), and an electrode (50). In one embodiment, the electrode (50) can lie adjacent to the second surface (22) and include, a barrier layer (54) lying between a conductive layer (56) and a metal-containing layer (52), wherein the metal-containing layer (52) includes a first metallic element and not a second metal element, and the barrier layer (54) includes the second metal element and not the first metallic element. In another embodiment, an adhesion layer (52) and a conductive layer (56) can each include a metallic element, and lie immediately adjacent to a barrier layer (54). In still another embodiment, a process for forming an electronic device can include removing a portion of the substrate (12) opposite a primary surface (14).

Abstract: An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to ?Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

Abstract: An electronic device can include a substrate (12) having a primary surface (14), a second surface (16, 22) opposite the primary surface (14), and an electrode (50). In one embodiment, the electrode (50) can lie adjacent to the second surface (22) and include, a barrier layer (54) lying between a conductive layer (56) and a metal-containing layer (52), wherein the metal-containing layer (52) includes a first metallic element and not a second metal element, and the barrier layer (54) includes the second metal element and not the first metallic element. In another embodiment, an adhesion layer (52) and a conductive layer (56) can each include a metallic element, and lie immediately adjacent to a barrier layer (54). In still another embodiment, a process for forming an electronic device can include removing a portion of the substrate (12) opposite a primary surface (14).

Abstract: An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to ?Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

Abstract: An antistatic sheet material and package formed therefrom is provided. The laminated sheet material includes a first inner layer which is preferably a coextruded film having a polyolefin ply and second copolymer ply of ethylene-acrylic acid copolymer, ethylene vinyl acetate copolymer, or blends thereof, a second intermediate layer such as a polyester film having an electrically conductive material thereon, and an outer layer of an antistatic material. The laminate may be formed by hot roll lamination or an adhesive may be used between the first and second layers.