Abstract: Examples disclosed herein relate to storage drive management. Some examples disclosed herein a storage controller may adjust failure criteria for a storage drive and determine whether to fail the storage drive based on the adjusted failure criteria. The storage controller may adjust the failure criteria based on various factors, such as the quantity of input/output (I/O) command abort attempts corresponding to the storage drive issued by a host device.

Abstract: Examples disclosed herein relate to variable cache flushing. Some examples disclosed herein a storage controller may detect a cache flush failure and, in response, may execute a first reattempt of the cache flush after a first time period has elapsed. The storage controller may adjust durations of time periods between subsequent reattempts of the cache flush based on various factors.

Abstract: Examples disclosed herein relate to variable cache flushing. Some examples disclosed herein a storage controller may detect a cache flush failure and, in response, may execute a first reattempt of the cache flush after a first time period has elapsed. The storage controller may adjust durations of time periods between subsequent reattempts of the cache flush based on various factors.

Abstract: Examples disclosed herein relate to storage drive management. Some examples disclosed herein a storage controller may adjust failure criteria for a storage drive and determine whether to fail the storage drive based on the adjusted failure criteria. The storage controller may adjust the failure criteria based on various factors, such as the quantity of input/output (I/O) command abort attempts corresponding to the storage drive issued by a host device.

Abstract: Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations associated with dynamic and static power related parameters of a circuit design. The power characterizations can be determined prior to circuit design optimizations, stored and utilized during circuit design optimizations.

Abstract: In one embodiment, the present invention relates to a system for generating an artwork representation according to a circuit fabrication process. The system comprises a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of the plurality of circuit cells is defined by a sub-mask for a respective logical device according to the circuit fabrication process; an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and the cell library; and an artwork generator that generates an artwork representation that defines a mask for etching of the generated circuit layout according to the circuit fabrication process.

Abstract: A process is shown for determining crossover current in a circuit design. One or more static CMOS gates are identified within the circuit design. One or more widths of at least one of a P-stack and N-stack associated with the CMOS gates are then determined. A voltage slope at the input of, and a capacitive load at the output of, one or more of the nodes are also determined. Crossover current, per static CMOS gate, is estimated based on the widths, the voltage slope and capacitive load. An overall crossover current is determined by summing individual gate-level crossover currents. The circuit design may be optimized for power consumption, for example, by modifying design elements of the circuit design while monitoring overall crossover current.

Abstract: A set of discrete transistor sizes spread in an exponential manner over a specified range is the basis for adjusted transistor sizes used to optimize a circuit. One of the discrete transistor sizes may be the original transistor size or other starting point for the optimization.

Abstract: A process is shown for determining crossover current in a circuit design. One or more static CMOS gates are identified within the circuit design. One or more widths of at least one of a P-stack and N-stack associated with the CMOS gates are then determined. A voltage slope at the input of, and a capacitive load at the output of, one or more of the nodes are also determined. Crossover current, per static CMOS gate, is estimated based on the widths, the voltage slope and capacitive load. An overall crossover current is determined by summing individual gate-level crossover currents. The circuit design may be optimized for power consumption, for example, by modifying design elements of the circuit design while monitoring overall crossover current.

Abstract: A process for processing a circuit design. One or more critical design paths of the circuit design are determined. These paths may for example be determined relative to timing and/or current utilization. Design elements of the paths may be grouped by type (e.g., FETs, wires). The circuit design may be optimized by processing a reduced set of design elements as determined by the critical paths and grouping. Optimization may include modifying FET design element width, or a routing path of a wire design element, along a critical path of the design, and comparing the new optimization relative to preselected design goals such as timing and power consumption.

Abstract: In one embodiment, the present invention relates to a system for generating an artwork representation according to a circuit fabrication process. The system comprises a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of the plurality of circuit cells is defined by a sub-mask for a respective logical device according to the circuit fabrication process; an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and the cell library; and an artwork generator that generates an artwork representation that defines a mask for etching of the generated circuit layout according to the circuit fabrication process.

Abstract: The present invention includes a system for and a method of identifying the location of contact pads on interconnect layers of printed circuit boards or metal layers of integrated circuits. The invention groups the conductive surfaces into rectangular areas and applies a mask to the identified rectangular areas by aligning a corner of the mask with the corresponding corner of the rectangular area. Once aligned, the remaining corners of the mask are checked to see whether there is an underlying conductive material present at all corners thereby identifying a suitable location for a contact pad. The invention further includes an alignment of alternate corners of the mask with the corresponding corner of the rectangular area if previous attempts to identify a contact pad were unsuccessful.

Abstract: The present invention includes a system for and a method of identifying the location of contact pads on interconnect layers of printed circuit boards or metal layers of integrated circuits. The invention groups the conductive surfaces into rectangular areas and applies a mask to the identified rectangular areas by aligning a corner of the mask with the corresponding corner of the rectangular area. Once aligned, the remaining corners of the mask are checked to see whether there is an underlying conductive material present at all corners thereby identifying a suitable location for a contact pad. The invention further includes an alignment of alternate corners of the mask with the corresponding corner of the rectangular area if previous attempts to identify a contact pad were unsuccessful.