Abstract: A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynamic random access memory array provides additional buffering capability. Input and output FIFOs are connected to the data and address bussed of the digital signal processor. The control of the digital signal processor is via a host processor connected to the digital signal processor by a serial communication link.

Abstract: Solid state electronic cameras are made modular so that replacement of inoperative CCD imagers can be done quickly and inexpensively by storing in the camera heads the operating parameters of each of a variety of imagers such as charge coupled device imagers. A camera head with a replacement imager communicates to a resident controller the parameters of the replacement imager selected. Operating parameters such as clock pulse signals may, in addition, be varied as to pulse width and frequency. The parameters are stored in an address set in a look up table in association with imager identifications.