Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.

Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.

Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.

Abstract: A peak detector circuit employs a line receiver of the ECL type, with the analog input signal to be tracked as a receiver input. The other receiver input is connected to the circuit output. A capacitor connects the output node of the circuit to threshold reference voltage input. The capacitor is charged through a resistor from the output of the line receiver when the input signal exceeds the voltage on the output node, and the capacitor discharges to the reference input through this resistor and another resistor connecting the receiver output to the reference input. The output voltage tracks the peaks of the input signal. Oscillation of the receiver is avoided by using a threshold reference greater than zero. The dynamic range of the output can be extended to a level higher than that of ECL levels by summing the thresholds of a number of these detectors, using an operational amplifier.

Abstract: Transceiver apparatus includes a transmitter circuit constructed with either emitter coupled logic (ECL) circuitry or programmable array logic circuitry, and a receiver circuit constructed with ECL circuitry. The transmitter circuit encodes a binary data signal received for transmission as a three-level modified duobinary encoded data signal and the receiver circuit decodes the received three-level encoded data signal to provide a binary data signal corresponding to the data signal received at the transmitter circuit for transmission. Both the transmitter and receiver circuits include features enabling transmitting and receiving high data-rate data signals.

Abstract: In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage-controlled oscillator in response to the difference in phase between the incoming data signal and the clock oscillator output. A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output. A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to see an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal.

Abstract: Several embodiments of an electronic calculating apparatus and wallet enclosure are described. The apparatus is provided with a side-located battery compartment for providing, in combination with the enclosure, a very convenient and useful, relatively thin assembly. The enclosure comprises two flap members. A first one of the flap members is adapted for supporting the apparatus. The other is adapted for folding over in facing relationship with the first. In each of the embodiments the first flap member is provided with an interior wall member. In one embodiment, the apparatus is separably inserted and supported in a pocket formed by the interior wall member. Keys which extend from the face of the apparatus for inserting numbers and the like project through keyholes provided in the interior wall member. In another embodiment, the apparatus is provided with engaging members which extend outwardly from the ends thereof.